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參數資料
| 型號： | TFP403PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 496K |
| 代理商： | TFP403PZPG4 |
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A DECEMBER 2000 REVISED OCTOBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RSVD
42
DO
Reserved. Must be tied high for normal operation
RSVD
9296
AI
Reserved. See TFP501 data sheet for intended future use.
RxC+
89
AI
Clock positive receiver input—Positive side of reference clock. TMDS low voltage signal differential input pair
RxC
90
AI
Clock negative receiver input—Negative side of reference clock. TMDS low voltage signal differential input
pair
Rx0+
86
AI
Channel-0 positive receiver input—Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0
87
AI
Channel-0 negative receiver input—Negative side of channel-0. TMDS low voltage signal differential input
pair.
Rx1+
83
AI
Channel-1 positive receiver input—Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Rx1
84
AI
Channel-1 negative receiver input—Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+
80
AI
Channel-2 positive receiver input—Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2 control signals in blank.
Rx2
81
AI
Channel-2 negative receiver input—Negative side of channel-2 TMDS low voltage signal differential input
pair.
SCDT
8
DO
Sync detect—Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP403 monitors the state DE to determine link activity. SCDT can be tied externally to
PDO to power down the output drivers when the link is inactive.
High: Active link
Low: Inactive link
ST
3
DI
Output drive strength select—Selects output drive strength for high or low current drive. (See dc specifications
for IOH and IOL vs ST state.)
High : High drive strength
Low : Low drive strength
STAG
7
DI
Staggered pixel select—An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers
the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
High : Normal simultaneous even/odd pixel output
Low: Time staggered even/odd pixel output
VSYNC
47
DO
Vertical sync output
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