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參數資料
| 型號： | TFP403PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 5/20頁 |
| 文件大小： | 496K |
| 代理商： | TFP403PZPG4 |
TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A DECEMBER 2000 REVISED OCTOBER 2002
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TFP403 TMDS input levels and input impedance matching (continued)
_
+
Internal
Termination at 50
AVDD
DVI Compliant Cable
DATA
TI TFP403
Receiver
DVI
Transmitter
Current
Source
Figure 12. TMDS Differential Input and Transmitter Connection
1/2 VID
AVCC
AVCC 1/2 VID
+ 1/2 VID
1/2 VID
VID
a ) Single-Ended Input Signal
b) Differential Input Signal
Figure 13. TMDS Inputs
TFP403 modes of operation
The TFP403 provides systems design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PANEL
PIXEL RATE
ODCK LATCH
EDGE
ODCK
DFO
PIXS
OCK_INV
TFT or 16-bit DSTN
1 pix/clock
Falling
Free run
0
TFT or 16-bit DSTN
1 pix/clock
Rising
Free run
0
1
TFT
2 pix/clock
Falling
Free run
0
1
0
TFT
2 pix/clock
Rising
Free run
0
1
24-bit DSTN
1 pix/clock
Falling
Gated low
1
0
NONE
1 pix/clock
Rising
Gated low
1
0
1
24-bit DSTN
2 pix/clock
Falling
Gated low
1
0
24-bit DSTN
2 pix/clock
Rising
Gated low
1
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