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| 型號(hào)： | TFP403PZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大小： | 496K |
| 代理商： | TFP403PZPG4 |
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TFP403
TI PanelBus DIGITAL RECEIVER
SLDS125A DECEMBER 2000 REVISED OCTOBER 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
TFP403 output driver configurations
The TFP403 provides flexibility by offering various output driver features that can be used to optimize power
consumption, ground-bounce, and power-supply noise. The following sections outline the output driver features
and their effects.
Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and
SCDT, into a high-impedance state. The SCDT output which indicates link-disabled or link-inactive can be tied
directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected.
An internal pullup on the PDO pin will default the TFP403 to the normal nonpower down output drive mode if
left unconnected.
Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP403 allows for
selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for the
values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times
the drive as the low output drive strength.
Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period
is 2Tpix when in 2-pixel/clock mode.)
Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP403
drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce
and EMI.
Power Management. The TFP403 offers several system power management features.
The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,
all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device
circuitry remains active
The TFP403 power down (PD = low) is a complete power down in that it powers down the digital core, the analog
circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the
PD input. The TFP403 will not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullup so if left unconnected they will default the TFP403 to normal operating
modes.
Sync Detect. The TFP403 offers an output, SCDT to indicate link activity. The TFP403 monitors activity on DE
to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the
TFP403 considers the link inactive and SCDT is driven low. The SCDT goes high immediately after the first
transition on DE. The SCDT again becomes low when no more transitions are seen after 218 ocillator clocks.
SCDT can be used to signal a system power management circuit to initiate a system power down when the link
is considered inactive. The SCDT can also be tied directly to the TFP403 PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power down, the analog inputs are ignored and the SCDT state does not change. An external system
power management circuit to drive PD is preferred.
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