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參數(shù)資料
| 型號： | THS1041IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
23
www.ti.com
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 35 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-Vp-p span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
reference output at VREF to 0.75 V. Tying MODE to AVDD then sets the REFT and REFB voltages via the internal
reference generator for a 1.5-Vp-p ADC input range.
If a transformer is used to generate the differential ADC input from a single-ended signal, then the CLAMPOUT
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AVDD.
AIN+
AIN
VREF = 0.75 V
REFB
MODE
REFSENSE
AVDD
1.875 V
1.125 V
1.875 V
1.125 V
1.5 V
REFT
5 k
10 k
0.1
F
10
F
20 pF
20
20
0.1
F
0.1
F
10
F
Figure 35. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 36 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for
the AIN pin and also, via a buffered potential divider; the 0.75 VREF voltage required to set the input range
to 1.5 Vp-p MODE is tied to AVDD to set internal ADC references configuration.
AIN+
AIN
REFT
MODE
REFB
2 V
0.5 V
1.25 V
VREF
AVDD
10 k
_
+
REFSENSE
AVDD
15 k
(0.75 V)
1.25
Source
0.1
F
10
F
0.1
F
0.1
F
20 pF
20
20
10
F
Figure 36. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
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