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參數資料
| 型號： | THS1041IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 20/41頁 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
27
www.ti.com
PRINCIPLES OF OPERATION
digital control registers
The THS1041 contains two clamp registers and a control register for user programming of THS1041 operation.
Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the
previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01
clamp register 2, and 10 the control register. The clamp registers and control registers are write only registers,
and stored values cannot be read on the I/O data bus.
Table 2. Register Map
ADDRESS
DESCRIPTION
DEF
W
BIT
ADDRESS
I/O[9:8]
DESCRIPTION
DEF
(HEX)
W
B7
B6
B5
B4
B3
B2
B1
B0
00
Clamp register 1
00
W
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
01
Clamp register 2
00
W
DAC[9]
DAC[8]
10
Control register
01
W
CLDIS
TWOC
CLINT
PDWN
PGA[2]
PGA[1]
PGA[0]
11
Reserved
Do not write to register 11
Table 3. Register Contents
REGISTER
BIT NO
BIT NAME(S)
DEFAULT
DESCRIPTION
2:0
PGA[2:0]
001
PGA gain:
000 = 0.5
001 = 1.0 (default value)
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0
Control register
I/O[9:8] = 10
3
PDWN
0
Power down
0 = THS1041 powered up
1 = THS1041 powered down
I/O[9:8] = 10
4
CLINT
0
Clamp voltage internal/external
0 = external analog clamp voltage from CLAMPIN pin
1 = from onboard DAC (see clamp register)
5
TWOC
0
Output format
0 = unsigned binary
1 = twos complement
6
CLDIS
0
CLAMPOUT pin disable (for power saving)
0 = Enable
1 = Disable
7
Unused
Clamp register 1
I/O[9:8] = 00
7:0
DAC[7:0]
0
Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp voltage = REFB
DAC[9:0] = 3Fh: Clamp voltage = REFT
Clamp register 2
7:2
Unused
Clamp register 2
I/O[9:8] = 01
1:0
DAC[9:8]
0
Clamp DAC voltage
(DAC[9] = MSB)
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