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參數資料
| 型號： | THS1041IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 37/41頁 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
5
www.ti.com
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 Vpp and 2 Vpp, PGA = 1X, TA = Tmin to Tmax (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD
Supply voltage
3
3.6
V
DVDD
Supply voltage
3
3.6
V
ICC
Operating supply current
See Note 4
34
42
mA
PD
Power dissipation
See Note 4
103
125
mW
PD(STBY)
Standby power
75
W
Power up time for all references from standby, t(PU)
10
F bypass
770
s
Wake-up time, t(WU)
See Note 5
45
s
REFT, REFB internal ADC reference voltages outputs (MODE = AVDD or AVDD/2) (See Note 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference voltage top, REFT
VREF = 0.5 V
AVDD = 3 V
1.75
V
Reference voltage top, REFT
VREF = 1 V
AVDD = 3 V
2
V
Refence voltage bottom, REFB
VREF = 0.5 V
AVDD = 3 V
1.25
V
Refence voltage bottom, REFB
VREF = 1 V
AVDD = 3 V
1
V
Input resistance between REFT and REFB
1.4
1.9
2.5
k
VREF (on-chip voltage reference generator)
PARAMETER
MIN
TYP
MAX
UNIT
Internal 0.5-V reference voltage (REFSENSE = VREF)
0.45
0.5
0.55
V
Internal 1-V reference voltage (REFSENSE = AGND)
0.95
1
1.05
V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2 or AVDD)
7
14
21
k
dc accuracy
PARAMETER
MIN
TYP
MAX
UNIT
Resolution
10
Bits
INL
Integral nonlinearity (see definitions)
1.5
±0.75
1.5
LSB
DNL
Differential nonlinearity (see definitions)
0.9
±0.3
1
LSB
Zero error (see definitions)
1.5
0.7
1.5
%FSR
Full-scale error (see definitions)
3
2.2
3
%FSR
Missing code
No missing code assured
NOTES:
4. A 1 dBFS 10-KHz triangle wave is applied at AIN+ and AIN. Internal bandgap reference and ADC reference are enabled,
CLAMPOUT is set to AVDD/2. ADC conversions are taking place during power measurements at 40 MSPS. A CLAMPOUT load or
VREF load may result in additional current.
5. Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down and an applied 40-MHz clock. Circuits that need to
power up are the bandgap, bias generator, ADC, and SHPGA.
6. External reference values are listed in the Recommended Operating Conditions Table.
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