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| 型號(hào)： | THS1041IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 24/41頁(yè) |
| 文件大小： | 810K |
| 代理商： | THS1041IPWRG4 |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
30
www.ti.com
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum IREF.
driving REFT and REFB (external ADC references, MODE = AGND)
AVDD
AGND
AVDD
AGND
2 k
REFT
REFB
To ADC Core
Figure 46. Equivalent Circuit of REFT and REFB Inputs
designing the dc clamp
Figure 38 shows the basic operation of the clamp circuit with the analog input AIN+ coupled via an RC circuit.
AIN must be connected to a dc source whose voltage level keeps the THS1041 differential input within the ADC
input range. The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or
by programming the on-chip clamp DAC.
(Note that it is possible to reverse the AIN+ and AIN connections if signal inversion is also required. The
following section assumes that the signal is coupled to AIN+ and that AIN is connected to a suitable dc bias
level).
initial clamp acquisition time
Acquisition time is the time required to reach the target clamp voltage at AIN+ when the clamp switch SW1 is
closed for the first time. The acquisition time is given by
T
ACQ +
C
IN
R
lN
ln
V
C
V
E
where VC is the difference between the dc level of the input VIN and the target clamp output voltage, VClamp.
VE is the difference between the ideal VC and the actual VC obtained during the acquisition time. The maximum
tolerable error depends on the application requirements.
For example, consider clamping an incoming video signal that has a black level near 0.3 V to a black level of
1.3 V at the THS1041 AIN+ input. The voltage VC required across the input coupling capacitor is thus
1.3 0.3 = 1 V. If a 10 mV or less clamp voltage error VE gives acceptable system operation, the source
resistance RIN is 20 and the coupling capacitor CIN is 1 F, then the total clamp pulse duration required to
reach this error is:
TACQ = 1 F × 20 × ln(1/0.01) = 92 s (approximate)
(16)
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