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參數(shù)資料
型號(hào)： TLV320AIC22PTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： ROHS COMPLIANT, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 16/55頁(yè)
文件大小： 782K
代理商： TLV320AIC22PTR
TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control register address and data (continued)
0
1
8
7
654
32
10
11
12
13
14
15
9
MSB
LSB
Control Register Data
Unused
NOTES: A. If the register address is 0x00h, then no register will be updated.
B. The default condition is for control information to be updated every frame. If control information is not to be updated every frame,
then register 17 can be programmed to cause the control slots to appear with N frames of empty control slots between them. The
contents of register 17 is equal to N. In this condition, the data in slots 0 and 1 that appear in the N frames between frames with valid
control slots are ignored. The default setting for register 17 is 0; control slots will appear in every frame. After register 17 is
programmed with a nonzero value, the first sequence will have N – 1 frames with empty control slots.
Figure 6. Bit Assignment and Definition for Slot-1 Word
ADC data word
A data word occupies one time slot and is 16 bits long. The ADC data word (output on DOUT) can be any of
the following:
D Data-valid flag + 15 bits of linear data
D 16 bits of linear data (no data-valid flag)
D Data-valid flag + A-law or -law coded PCM data
D A-law or -law coded PCM data (no data-valid flag)
The selection of linear, A-law, or
-law coding is programmed in register 15, bits 6 and 7. The selection for
providing the data-valid flag bit is programmed in register 13. See the ADC and DAC channel data section for
a detailed description of the valid and invalid data.
The structure of a data word is shown in Figure 7 and Figure 8.
0
1
8
7
654
32
10
11
12
13
14
15
9
Data-Valid
Flag Bit
15-Bit Codec Data, (Linear Mode)
MSB
LSB
NOTE: The MSB of the codec data is bit 14 for linear mode and bit 7 for A-law and
-law.
8-Bit Codec Data (A-Law,
-Law PCM Mode)
Zeros When A-Law or
-Law PCM
Mode Selected
Figure 7. Bit Assignment and Definition for ADC Data Word When the Data-Valid Flag is Enabled
Figure 7 describes the ADC data-word format when the data-valid flag is used. The data-valid flag is positioned
in bit 15 (the MSB of the data word) and is transmitted first. The flag bit is enabled by programming register 13.
Bit 14 of the data word is the most significant bit of the 15-bit codec data when the linear mode is selected and
the data-valid flag is enabled.
When A-law or
-law PCM coding is selected, the 8 bits of the PCM data are located, with the MSB in the bit 7
location and the LSB in the bit 0 location of the data word. Unused bits are zero when PCM coding is enabled.
Bit 15 always is the data-valid flag for both the PCM and linear coding when the data-valid flag is enabled. The
selection of linear, A-law, or
-law coding is programmed in register 15, bits 6 and 7.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TLV320AIC23_06 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier
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TLV320AIC23B_06 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier
TLV320AIC23BGQE 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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