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參數資料
| 型號： | TLV320AIC22PTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-48 |
| 文件頁數： | 25/55頁 |
| 文件大小： | 782K |
| 代理商： | TLV320AIC22PTR |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ADC and DAC channel data (continued)
On the receive side (DAC), the DSP can use the same flag bits it extracts from the DOUT bit stream. It can use
it as the DATA request signal for the DAC of the same codec and send the DAC data on DIN during the next
frame.
The valid data appears in the Ith or (I + N)th frame. For every D number of valid ADC data bytes, the ADC
transmits a valid data word in the (I + 1)th frame, for N times, and in the Ith frame for (D – N) times. I, N, and
D are the values used for the (I + N/D) divider.
For this example where MCLK = 32.768 MHz, I + N/D = 4 + 4/9 and the sample rate is 14.4 kHz, the ADC data
will appear in the fifth frame four times and in the fourth frame five times, repeating. The valid data bit/FSYNC
pattern will be (in terms of frame syncs):
4, 5, 4, 5, 4, 5, 4, 5, 4
Then, this sequence repeats. See Table 12 for I, N, and D derivations for this example.
Table 12. I, N, and D Derivation for 32.768-MHz Clock and 14.4-kHz Sampling Rate
PARAMETER OR VARIABLE
EQUATION
VALUE
MCLK
None
32.768 MHz (given)
BCLK
MCLK/2
16.384 MHz
FSYNC
BCLK/256
64 kHz
Sample rate
MCLK/(512 x (I + N/D))
14.4 kHz (given)
I + N/D
MCLK/(512 x sample rate)
4.4444
I
4
N
4
D
9
Example 3: This example is for the case where codec 1 and codec 2 have different sampling rates. If an 8-kHz
sampling rate is needed on codec 1, then codec 1 sends a valid data word every eighth frame for its particular
time slot. If a 16-kHz sampling rate is needed on codec 2, then codec 2 sends a valid data word every fourth
frame for its particular time slot. Table 13 shows the derivation of the parameters for each codec. A 32.768-MHz
master clock is assumed.
Table 13. I, N, and D Derivation for 32.768-MHz Clock, With an 8-kHz Sampling Rate for
Codec 1 and a 16-kHz Sampling Rate for Codec 2
PARAMETER OR
VARIABLE
CODEC
EQUATION
VALUE
MCLK
–
None
32.768 MHz (given)
BCLK
–
MCLK/2
16.384 MHz
FSYNC
–
BCLK/256
64 kHz
Sample rate
Codec 1
MCLK/[512 x (I + N/D)]
8 kHz (given)
I + N/D
Codec 1
MCLK/(512 x sample rate)
8
I
Codec 1
8
N
Codec 1
0
D
Codec 1
9
Sample rate
Codec 2
MCLK/[512 x (I + N/D)]
16 kHz (given)
I + N/D
Codec 2
MCLK/(512 x sample rate)
4
I
Codec 2
4
N
Codec 2
0
D
Codec 2
9
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