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參數資料
| 型號： | TLV320AIC22PTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-48 |
| 文件頁數： | 28/55頁 |
| 文件大小： | 782K |
| 代理商： | TLV320AIC22PTR |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
register programming using the I2C bus (continued)
SDA: I2C-bus serial address/data input/output. This is a bidirectional pin used to transfer register control
address and data into and out of the codec. It is an open-drain terminal and, therefore, requires a pullup
resistor to DVDD (typical 10 k
for 100 kHz).
AD0: In I2C mode, AD0 is a chip address bit.
AD1: In I2C mode, AD1 is a chip address bit.
Pins AD0 and AD1 form the partial chip address. The upper 5 bits (A6:A2) of the 7-bit address field must be
11100. To communicate with a TLV320AIC22, the LSBs of the chip address field (A1:A0), which is the first byte
sent to the TLV320AIC22, should match the settings of the AD1, AD0 pins. For normal data transfer, SDA is
allowed to change only during SCL low. Changes during SCL high are reserved for indicating the start and stop
conditions. Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must
remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted
as a start or stop condition.
Table 14. I2C Bus Status
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain high
B
Start data transfer
A high-to-low transition of the SDA line while the clock (SCL) is high determines a start condition. All
commands must proceed from a start condition.
C
Stop data transfer
A low-to-high transition of the SDA line while the clock (SCL) is high determines a stop condition. All
operations must end with a stop condition.
D
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable for the
duration of the high period of the clock signal.
I2C-bus conditions
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit data and each data transfer is initiated with a start condition and terminated with a stop condition. The host
device determines the number of data bytes transferred between the start and stop conditions. When
addressed, the TLV320AIC22 generates an acknowledge after the reception of each byte. The host device
(microprocessor or DSP) must generate an extra clock pulse which is associated with this acknowledge bit.
The TLV320AIC22 must pull the SDA line down during the acknowledge clock pulse, so that the SDA line is
stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken
into account. During reads, a host device must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (TLV320AIC22)
must leave the data line high to enable the host device to generate the stop condition.
A0
R/W
00
Slave Address
00
SCL
SDA
Start
A6
A5
A4
ACK
R7
R6
R5
R0
ACK
D7
D6
D5
D0
ACK
Stop
Register Address
Data
Figure 16. I2C-Bus Write to TLV320AIC22
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