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參數資料
| 型號： | TLV320AIC22PTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LQFP-48 |
| 文件頁數： | 9/55頁 |
| 文件大小： | 782K |
| 代理商： | TLV320AIC22PTR |
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TLV320AIC22
DUAL VOIP CODEC
SLAS281B – JULY 2000 – REVISED JUNE 2002
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
DAC channel
The DAC channel consists of an interpolation filter, a sigma-delta DAC, low-pass filter, and a programmable gain
amplifier. The DAC is an oversampling sigma-delta modulator. The DAC performs high-resolution, low-noise
DAC, using oversampling sigma-delta techniques.
The DAC receives 16-bit data words (2s complement) from the host via the serial-port interface. Data is latched
on the falling edge of BCLK. The MSB of the digital data is transmitted to the DAC first, ending with the LSB
as the last bit.
The data is converted to an analog voltage by the sigma-delta DAC, composed of a digital interpolation filter
and a digital modulator. The interpolation filter resamples the digital data at a rate of N times the incoming sample
rate, where N is the oversampling ratio. The high-speed data output from this filter then is applied to the
sigma-delta DAC.
The DAC output then is passed to an internal, low-pass filter to complete the signal reconstruction, resulting
in an analog signal. This analog signal then is buffered and amplified by a differential output driver capable of
driving the required load. The gain of the DAC output amplifier is programmed in register 4 for codec 1 and
register 9 for codec 2.
analog and digital loopback
The test capabilities include an analog loopback and digital loopback. The loopbacks allow the user to test the
ADC/DAC channels and can be used for in-circuit system-level tests. The digital loopback feeds the ADC output
to the DAC input on the device. The analog loopback loops the DAC output back into the ADC input.
power down and reset
When the power-down pin (PWRDWN) is pulled high, the device goes into a power-down mode, where the
required analog power-supply current drops to approximately 100
A and the digital power-supply current drops
to approximately 2 mA. This is called the hardware power-down mode. The serial interface and I2C interface
still are enabled. All register values are sustained and the device resumes full-power operation without
reinitialization when PWRDWN is pulled low again. PWRDWN resets the counters only and preserves the
programmed register contents. After the PWRDWN pin has been pulled low, the user must wait at least two
frame syncs before communicating control or conversion information.
Software control can be used to power down individual codecs. Each codec is composed of an ADC, DAC, and
a digital filter. Codec power down resets all internal counters, but leaves the contents of the programmable
control registers unchanged. Analog circuitry and the analog power-supply current are not affected when
programming codec power-down mode. Codec power down is achieved by programming register 2 for codec
1 and register 7 for codec 2.
An analog master power down also can be initiated via software control by programming register 14. Analog
master power down is used to power down all of the analog circuitry within the device. This mode is similar to
hardware power down in that the required analog power-supply current drops to approximately 100
A.
Table 1 shows the state of the pins during codec power down and hardware power down.
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| TLV320AIC23 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STereo Audio CODEC, 8- to 96kHz, With Integrated Headphone Amplifier |
| TLV320AIC23_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier |
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| TLV320AIC23BGQE | 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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