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參數資料
型號: TLV320AIC32IRHB
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, PLASTIC, QFN-32
文件頁數: 15/76頁
文件大小: 1124K
代理商: TLV320AIC32IRHB
www.ti.com
AUDIO DATA CONVERTERS
AUDIO CLOCK GENERATION
K*R/P
2/Q
PLL_CLKIN
CODEC
CODEC_CLKIN
PLL_OUT
K = J.D
J = 1,2,3,…..,62,63
D= 0000,0001,….,9998,9999
R= 1,2,3,4,….,15,16
P= 1,2,….,7,8
Q=2,3,…..,16,17
MCLK BCLK
CLKDIV_IN
PLL_IN
WCLK= Fsref/Ndac
ADC_FS
DAC_FS
Ndac=1,1.5,2,…..,5.5,6
DAC DRA => Ndac = 0.5
CODEC_CLK=256*Fsref
CLKDIV_OUT
1/8
PLLDIV_OUT
CLKDIV_CLKIN
SLAS479B – AUGUST 2005 – REVISED AUGUST 2006
OVERVIEW (continued)
The TLV320AIC32 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further below.
The data converters are based on the concept of an Fsref rate that is used internal to the part, and it is related
to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, Fsref will be
either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with
additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and
DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise
being generated.
The sampling rate of the ADC and DAC can be set to Fsref/NDAC or 2
×Fsref/NDAC, with NDAC being 1, 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.
The audio converters in the TLV320AIC32 need an internal audio master clock at a frequency of 256
×Fsref,
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC32 is shown in Figure 24.
Figure 24. Audio Clock Generation Processing
22
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相關代理商/技術參數
參數描述
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