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參數資料
| 型號： | TMDS442PNPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數： | 2/45頁 |
| 文件大小： | 1977K |
| 代理商： | TMDS442PNPRG4 |
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SWITCHING CHARACTERISTICS
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
TMDS DIFFERENTIAL PINS (Y/Z)
tPLH
Propagation delay time, low-to-high-level output
250
800
ps
tPHL
Propagation delay time, high-to-low-level output
250
800
ps
tr
Differential output signal rise time (20% - 80%)
80
240
ps
tf
Differential output signal fall time (20% - 80%)
80
240
ps
tsk(p)
Pulse skew (|tPHL – tPLH|)
(2)
50
ps
RT = 50
tsk(D)
Intra-pair differential skew, see Figure 7
75
ps
tsk(o)
Inter-pair channel-to-channel output skew(3)
150
ps
tsk(bb)
Bank-to-bank skew
300
ps
tsk(pp)
Part-to-part skew (4)
1
ns
ten
Enable time
20
ns
See Figure 8
tdis
Disable time
20
ns
tsx
TMDS Switch time
20
ns
tjit(pp)
Peak-to-peak output jitter from Y/Z(1), residual jitter
See Figure 9, Ai/Bi(1) = 165-MHz clock,
10
30
ps
Ai/Bi(2:4) = 1.65-Gbps HDMI pattern,
PRE = low
tjit(pp)
Peak-to-peak output jitter from Y/Z(2:4), residual jitter
48
74
ps
Input: 5m 28AWG HDMI cable,
Output: 3-Inch 8-mil trace width
tjit(pp)
Peak-to-peak output jitter from Y/Z(1), residual jitter
See Figure 9, Ai/Bi(1) = 225-MHz clock,
18
33
ps
Ai/Bi(2:4) = 2.25-Gbps HDMI pattern,
PRE = low
tjit(pp)
Peak-to-peak output jitter from Y/Z(2:4), residual jitter
56
71
ps
Input: 5m 28AWG HDMI cable,
Output: 3-Inch 8-mil trace width
CONTROL AND STATUS PINS (HPD_SINK, HPD, 5V_PWR, 5V_SINK)
tpd(HPD)
Propagation delay time
15
ns
tpd(5V)
Propagation delay time
15
ns
See Figure 8
tsx(HPD)
HPD Switch time
15
ns
CL= 10 pF, CL(DDC) = 100 pF
tsx(5V)
5-V Power switch time
15
ns
tsx
DDC Switch time
1
μs
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
Propagation delay time, low-to-high-level output
tPLH
204
459
ns
SCL_SINK/SDA_SINK to SCL/SDA
Propagation delay time, high-to-low-level
tPHL
35
140
ns
outputSCL_SINK/SDA_SINK to SCL/SDA
Propagation delay time, low-to-high-level output SCL/SDA to
tPLH
194
351
ns
SCL_SINK/SDA_SINK
See Figure 11, OVS = NC
Propagation delay time, high-to-low-level output SCL/SDA to
tPHL
35
140
ns
SCL_SINK/SDA_SINK
tr
Output signal rise time, SCL_SINK/SDA_SINK
500
800
ns
tf
Output signal fall time, SCL_SINK/SDA_SINK
20
72
ns
tr
Output signal rise time, SCL/SDA
796
999
ns
tf
Output signal fall time, SCL/SDA
20
72
ns
tset
Enable to start condition
100
ns
See Figure 12
thold
Enable after stop condition
100
ns
(1)
All typical values are at 25
°C and with a 3.3-V supply.
(2)
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
(3)
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when
inputs are tied together.
(4)
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or
between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same
temperature, and have identical packages and test circuits.
10
Copyright 2006–2007, Texas Instruments Incorporated
Product Folder Link(s): TMDS442
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