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| 型號： | TMX320F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 32/103頁 |
| 文件大小： | 1341K |
| 代理商： | TMX320F2810PBKAEP |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
XINTCNF2 register (continued)
Table 15. XINTCNF2 Register Bit Definitions (Continued)
BITS
TYPE
NAME
RESET
DESCRIPTION
7,6
R
WLEVEL
0,0
The current number of writes buffered are detectable as follows:
Level
Action
00
01
10
11
empty
1 value currently in the write buffer
2 values currently in the write buffer
3 values currently in the write buffer
The value in the write buffer may be 8-, 16-, or 32-bit data.
Note
: There may be a few cycle delay from when a value enters the write buffer
to the buffer level depth being updated.
8
R/W
MP/MC
Mode
On reset, this bit reflects the state of the XMP/MC input signal sampled at XRS.
The user can modify the state of this bit by writing a 1 or a 0 to this location. This
will be reflected on the XMP/MC output signal. This mode also affects ZONE 7 and
Boot ROM mapping as follows:
MP/MC = 1, microprocessor state
(XINTF ZONE 7 enabled, Boot ROM disabled).
MP/MC = 0, microcomputer state
(XINTF ZONE 7 disabled, Boot ROM enabled).
Note
: The XMP/MC input signal state is ignored after reset.
This bit, when low, will automatically grant a request to an external device driving
the XHOLD input signal low (XHOLDA output signal is driven low when request
granted). This bit, when set high, will not automatically grant a request to an
external device driving the XHOLD input signal low (XHOLDA output signal stays
high).
9
R/W
HOLD
0
If this bit is set, while XHOLD and XHOLDA are both low (external bus accesses
granted) then the XHOLDA signal is forced high (at the end of the current cycle)
and the exteranl interface is taken out of high-impedance mode.
On a reset XRS, this bit is set to zero. If on a reset the XHOLD signal is active-low,
then the bus and all signal strobes must be in high-impedance state and the
XHOLDA signal also driven active-low.
When HOLD mode is enabled and XHOLDA is active-low (external bus grant
active) then the core can still execute code from internal memory. If an access is
made to the external interface, then a not ready signal is generated and the core
is stalled until the XHOLD signal is removed.
10
R
HOLDS
XHOLD input
signal
This bit reflects the current state of the XHOLD input signal. It can be read by the
user to determine if an external device is requesting access to the external bus.
11
R
HOLDAS
XHOLDA input
signal
This bit reflects the current state of the XHOLDA output signal. It can be read by
the user to determine if the external interface is currently granting access to an
external device.
P
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相關代理商/技術參數 |
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| TMX320F2810PBKS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFAEP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
| TMX320F2810PGFS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2811GHHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
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