
SLUSAH9
– MARCH 2011
Light-Load Power Saving Features
The TPS51317 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range.
The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. This
saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off, the
converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as
well.
TPS51317 also provides a special light-load power saving feature, called ripple reduction. Essentially, it reduces
the on-time in SKIP mode to effectively reduce the output voltage ripple associated with using an all MLCC
capacitor output power stage design.
Power Sequences
Non-Tracking Startup
The TPS51317 can be configured for non-tracking application. When non-tracking is configured, output voltage is
regulated to the REFIN voltage which taps off the voltage dividers from the 2VREF. Either the EN pin or the V5IN
pin can be used to start up the device. The TPS51317 uses internal voltage servo DAC to provide a precise
1.6-ms soft-start time during soft-start initialization. (See
Figure 11)
Tracking Startup
TPS51317 can also be configured for tracking application. When tracking configuration is desired, output voltage
is also regulated to the REFIN voltage which comes from external power source. In order for TPS51317 to
differentiate between a non-tracking configuration or a tracking configuration, there is a minimum delay time of
260
s required between the time when the EN pin or the 5VIN pin is validated to the time when the REFIN pin
voltage can be applied, in order for the TPS51317 to track properly (see
Figure 12). The valid REFIN voltage
range is between 0.6 V to 2 V.
Protection Features
The TPS51317 offers many features to protect the converter power chain as well as the system electronics.
5-V Undervoltage Protection (UVLO)
The TPS51317 continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high enough
to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The converter
starts with approximately 4.3 V and has a nominal of 440 mV of hysteresis. If the 5-V UVLO limit is reached, the
converter transitions the phase node into a off function. And the converter remains in the off state until the device
is reset by cycling 5 V until the 5-V POR is reached (2.3-V nominal). The power input does not have an UVLO
function
Power Good Signals
The TPS51317 has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power good high
propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage condition
on V5IN or any other faults that require latch off action is detected.
Output Overvoltage Protection (OVP)
In addition to the power good function described above, the TPS51317 has additional OVP and UVP thresholds
and protection circuits.
An OVP condition is detected when the output voltage is approximately 120%
× VREFIN. In this case, the
converter de-asserts the PGOOD signals and performs the overvoltage protection function. The converter
remains in this state until the device is reset by cycling 5 V until the 5-V POR threshold (2.3 V nominal) is
reached.
Output Undervoltage Protection (UVP)
Output undervoltage protection works in conjunction with the current protection described in the
Overcurrentthe device latches OFF. Undervoltage protection can be reset only by EN or a 5-V POR.
Copyright
2011, Texas Instruments Incorporated
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