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參數(shù)資料
型號: TPS65950ZXNT
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝: 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù): 41/167頁
文件大?。?/td> 2566K
代理商: TPS65950ZXNT
HFCLKIN
CH0
CH1
032-065
12.2.3 32-kHz Input Clock
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
When the external clock signal is present on the HFCLKIN ball, it is possible to use this clock instead of
the internal RC oscillator and then synchronize the system on the same clock. The RC oscillator can then
go to idle mode.
Table 12-2 lists the input clock electrical characteristics of the HFCLKIN input clock.
Table 12-2. HFCLKIN Input Clock Electrical Characteristics
Parameter
Configuration Mode Slicer
Min(1)
Typ(2)
Max(3)
Unit
Frequency
19,
26, or
38.4
MHz
Startup time
LP/HP (sine wave)
4
s
Input dynamic range
LP/HP (sine wave)
0.3
0.7
1.45
VPP
BP/PD (square wave)
0
1.85(4)
Current consumption
LP
175
A
HP
235
BP/PD
39
nA
Harmonic content of input signal (with 0.7-VPP
LP/HP (sine wave)
–25
dBc
amplitude): second component
Voltage input high (VIH)
BP (square wave)
1
V
Voltage input low (VIL)
BP (square wave)
0.6
V
(1)
Min = Minimum value
(2)
Typ = Typical value
(3)
Max = Maximum value
(4)
Bypass input max voltage is the same as the maximum voltage provided for the I/O interface (IO.1P8V).
Table 12-3 lists the input clock timing requirements of the HFCLKIN input clock when the source is a
square wave.
Table 12-3. HFCLKIN Square Input Clock Timing Requirements With Slicer in Bypass
Name
Parameter
Description
Min(1)
Typ(2)
Max(3)
Unit
CH0
1/tC(HFCLKIN)
Frequency, HFCLKIN
19.2, 26, or 38.4
MHz
CH1
tW(HFCLKIN)
Pulse duration, HFCLKIN low or high
0.45*tC(HFCLKIN)
0.55*tC(HFCLKIN)
ns
CH3
tR(HFCLKIN)
Rise time, HFCLKIN(4)
0.05*tC(HFCLKIN)
ns
CH4
tF(HFCLKIN)
Fall time, HFCLKIN(4)
0.05*tC(HFCLKIN)
ns
(1)
Min = Minimum value
(2)
Typ = Typical value
(3)
Max = Maximum value
(4)
The capacitive load is 30 pF.
Figure 12-4 shows the timing of the HFCLKIN squared input clock.
Figure 12-4. HFCLKIN Squared Input Clock
A 32.768-kHz input clock (often abbreviated to 32-kHz) generates the clocks for the RTC. It has a low-jitter
mode where the current consumption increases for lower jitter. It is possible to use the 32-kHz input clock
with an external crystal or clock source. Depending on the mode, the 32K oscillator is configured as being
either:
An external 32.768-kHz crystal through the 32KXIN/32KXOUT balls (see Figure 12-5). This
configuration is available for master mode only (for more information, see Section 13, Timing
Requirements and Switching Characteristics).
Clock Specifications
135
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