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參數資料
型號: TPS65950ZXNT
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝: 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數: 55/167頁
文件大?。?/td> 2566K
代理商: TPS65950ZXNT
13.4.2 TDM Data Format
I2S.SYNC
I2S.CLK
I2S.DIN
I2S.DOUT
23 22
1
0
23
22
1
0
23
22
1
0
23 22
1
0
23 22
1
0
23 22
1
0
23 22
1
0
23
22
1
0
Channel1
Channel2
Channel3
Channel4
T1
T3
T4
T5
T2 T2
T2
T0
T1
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
8dummy
bits
032-080
TPS65950
Integrated Power Management/Audio Codec
SWCS032 – OCTOBER 2008
www.ti.com
Table 13-5. I2S Interface—Timing Requirements (continued)
Notation
Parameter
Min(1)
Max(2)
Unit
I1
tw(CLK)
Pulse duration, I2S.CLK high or low(4)
0.45 * P
0.55 * P
ns
I3
tsu(DIN-CLKH)
Setup time, I2S.DIN valid to I2S.CLK high
5
ns
I4
th(DIN-CLKH)
Hold time, I2S.DIN valid from I2S.CLK high.
5
ns
I6
tsu(SYNC-CLKH)
Setup time, I2S.SYNC valid to I2S.CLK high
5
ns
I7
th(SYNC-CLKH)
Hold time, I2S.SYNC valid from I2S.CLK high
5
ns
(4)
P = I2S.CLK period
The capacitive load for Table 13-6 is 7 pF.
Table 13-6. I2S Interface—Switching Characteristics
Notation
Parameter
Min(1)
Max(2)
Unit
Master Mode
I0
tc(CLK)
Cycle time, I2S.CLK(3)
1/64 * Fs
ns
I1
tw(CLK)
Pulse duration, I2S.CLK high or low(4)
0.45 * P
0.55 * P
ns
I2
td(CLKL-SYNC)
Delay time, I2S.CLK falling edge to I2S.SYNC transition
–10
10
ns
I5
td(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT transition
–10
10
ns
Slave Mode
I5
td(CLKL-DOUT)
Delay time, I2S.CLK falling edge to I2S.DOUT transition
0
20
ns
(1)
Min = Minimum value
(2)
Max = Maximum value
(3)
Fs = 8 to 48 kHz; 96 kHz for RX path only
(4)
P = I2S.CLK period
Table 13-7 and Table 13-8 assume testing over the recommended operating conditions (see Figure 13-4).
Figure 13-4. TDM Interface—TDM Master Mode
The timing requirements in Table 13-7 are valid on the following conditions of input slew and output load:
Rise and fall time range of inputs (SYNC, DIN) is t
R/tF = 1.0 ns/6.5 ns
Capacitance load range of outputs (CLK, SYNC, DOUT) is C
Load = 1 pF/30 pF
Table 13-7 lists the master mode timing requirements for the TDM interface.
Timing Requirements and Switching Characteristics
148
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