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參數資料
| 型號： | TS8388BVF |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 22/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BVF |
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29
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
In other terms:
– If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).
– If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However,
external TOD-TDR values may be dictated by total digital data skews between every TODs
(each digital data) and TDR: MCM Board, bonding wires and output lines lengths
differences, and output termination impedance mismatches.
The external (on board) skew effect has NOT been taken into account for the specification of the mini-
mum and maximum values for TOD-TDR.
8.1.4
Principle of Operation
The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA (aperture
delay) of typically 250 ps. The digitized data is available after 4 clock periods latency (pipeline delay
(TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD.
The Data Ready differential output signal frequency (DR, DRB) is half the external clock frequency, that
is it switches at the same rate as the digital outputs.
The Data Ready output signal (DR, DRB) switches on external clock falling edge after a propagation
delay TDR of typically 1320 ps.
A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available
for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain
applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without
Data Ready signal initialization, it is impossible to store the output digital data in a defined order.
8.2
Principle of Data Ready Signal Control by DRRB Input Command
8.2.1
Data Ready Output Signal Reset
The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level
(–1.8V). DRRB may also be tied to V
EE = -5V for Data Ready output signal Master Reset. So long DRRB
remains at logical low level, (or tied to V
EE = -5V), the Data Ready output remains at logical zero and is
independent of the external free running encoding clock.
The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical.
TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero
crossing point of the differential Data Ready output signal (DR, DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
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