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參數資料
| 型號： | TS8388BVF |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 24/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BVF |
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30
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
8.2.2
Data Ready Output Signal Restart
The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V).
DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at
DRRB rising edge instant:
The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW: The Data
Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay
time TDR = 1320 ps already defined here above.
The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH: The Data
Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay
TDR = 1320 ps.
Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding
to the first acquisition (N) after Data Ready signal restart (rising edge) is always strobed by the third ris-
ing edge of the data ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero
crossing point) to the rising or falling edge of the differential Data Ready signal (DR, DRB) (zero crossing
point).
For normal initialization of Data Ready output signal, the external encoding clock signal frequency and
level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10
Msps and consequently the clock cannot be stopped.
One single pin is used for both DRRB input command and die junction temperature monitoring. Pin
denomination will be DRRB/DIOD. On the former version denomination was DIOD. Temperature moni-
toring and Data Ready control by DRRB is not possible simultaneously.
8.3
Analog Inputs (V
IN) (VINB)
The analog input Full Scale range is 0.5V peak to peak (Vpp), or –2 dBm into the 50
termination
resistor.
In differential mode input configuration, that means 0.25V on each input, or ±125 mV around 0V. The
input common mode is ground.
The typical input capacitance is 3 pF for TS8388B in CQFP and CBGA packages.
The input capacitance is mainly due to the package.
8.3.1
Differential Inputs Voltage Span
Figure 8-1.
Differential Inputs Voltage Span
-125
125
[mV]
-250 mV
VIN
(VIN, VINB) =
±250 mV = 500 mV diff
500 mV
Full Scale
analog input
t
VINB
0V
250 mV
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