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參數資料
| 型號： | TS8388BVF |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 26/62頁 |
| 文件大小： | 1267K |
| 代理商： | TS8388BVF |
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32
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
No performance degradation (that is: due to timing jitter) is observed in this particular single-ended con-
figuration up to 1.2 Gsps Nyquist conditions (F
IN = 600 MHz).
This is true so long as the inverted phase clock input pin is 50
terminated very closely to one of the
neighboring shield ground pins, which constitutes the local Ground reference for the inphase clock input.
Thus the TS8388B differential clock input buffer will fully reject the local ground noise (and any capaci-
tively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise
sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50
termination resistor. Do not
exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50
termination resistor.
Figure 8-3.
Single-ended Clock Input (Ground common mode):
VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50
termination
resistor)
Note:
Do not exceed 10 dBm into the 50
termination resistor for single clock input power level.
8.4.2
Differential ECL Clock Input
The clock inputs can be driven differentially with nominal –0.8V/–1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a
power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing
tees can be used for offseting the common mode voltage to ECL levels.
Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to
ensure the signals to be 180 degrees out of phase especially at fast clock rates in the Gsps range.
Figure 8-4.
Differential Clock Inputs (ECL Levels)
50
(external or
on package)
1 M
0.4 pF
-0.5V
+0.5V
t
[V]
VCLK
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50
reverse termination
VCLK = 0V
VCLK
50
(external or
on package)
1 M
0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
-2V
50
reverse termination
-1.8V
-0.8V
[mV]
VCLK
t
VCLKB
Common mode = -1.3V
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