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參數資料
型號: TS8388BVF
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝: CERAMIC, QFP-68
文件頁數: 56/62頁
文件大小: 1267K
代理商: TS8388BVF
6
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
50
differentially terminated
0.54
0.660
V
Output levels (assuming VPLUSD = 0V)
75
open transmission lines:
4
–––
Logic “0” voltage
VOL
––
1.62
1.54
V
Logic “1” voltage
V
OH
0.88
0.8
V
Output levels (assuming VPLUSD = 0V)
75
differentially terminated:
4
–––
Logic “0” voltage
VOL
––
1.41
1.34
V
Logic “1” voltage
VOH
1.07
1–
V
Output levels (assuming V
PLUSD = 0V)
50
differentially terminated:
–––
Logic “0” voltage
V
OL
1, 2
6
1.40
1.32
1.25
V
Logic “1” voltage
V
OH
1, 2
6
1.16
1.25
1.10
V
Differential Output Swing
DOS
4
270
300
mV
Output level drift with temperature
4
1.6
mV/
°C
DC Accuracy (CBGA68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
T
J (typical) = 70°C
Differential nonlinearity
DNL-
1
0.6
0.4
lsb
Differential nonlinearity
DNL+
1
0.4
0.6
lsb
Integral nonlinearity
INL-
1
1.2
0.7
lsb
Integral nonlinearity
INL+
1
0.7
1.2
lsb
No missing codes
Guaranteed over specified temperature range
Gain
1, 2
90
98
110
%
Input offset voltage
1, 2
26
526
mV
Gain error drift
Offset error drift
4
100
40
125
50
150
60
ppm/
°C
ppm/
°C
DC Accuracy (CQFP68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
T
J (typical) = 70°C.
Differential nonlinearity
DNL-
1, 2
6
0.5
0.6
0.25
0.35
lsb
Differential nonlinearity
DNL+
1, 2
6
0.3
0.4
0.6
0.7
lsb
Table 5-3.
Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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