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參數資料
| 型號： | TS8388BVFSB/Q |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 19/47頁 |
| 文件大小： | 1230K |
| 代理商： | TS8388BVFSB/Q |
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26
TS8388BF
2144A–BDC–04/02
Differential Versus
Single-ended Analog
Input Operation
The TS8388BF can operate at full speed in either differential or single-ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier
stage, (preceeding the Sample and hold stage), which has been designed in order to be
entered either in differential mode or single-ended mode.
This is true so long as the out-of-phase analog input pin V
INB is 50 terminated very closely to
one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground
reference for the inphase analog input pin (V
IN).
Thus the differential analog input preamplifier will fully reject the local ground noise (and any
capacitively and inductively coupled noise) as common mode effects.
In typical single-ended configuration, enter on the (V
IN) input pin, with the inverted phase input
pin (V
INB) grounded through the 50 termination resistor.
In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, cen-
tered on 0V (or -2 dBm into 50
). The inverted phase input is at ground potential through the
50
termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or
clock inputs in differential mode.
Typical Single-ended
Analog Input
Configuration
Figure 28. Typical Single-ended Analog Input Configuration
Clock Inputs (CLK)
(CLKB)
The TS8388BF can be clocked at full speed without noticeable performance degradation in
either differential or single-ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,
which has been designed in order to be entered either in differential or single-ended mode.
Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor
spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.
Single-ended Clock
Input (Ground
Common Mode)
Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V
ECL levels, the TS8388BF clock buffer can manage a single-ended sinewave clock signal
centered around 0V. This is the most convenient clock input configuration as it does not
require the use of a power splitter.
No performance degradation (i.e.: due to timing jitter) is observed in this particular single-
ended configuration up to 1.2 GSPS Nyquist conditions (F
IN = 600 MHz).
50
(external)
1 M
3 pF
-250
250
500 mV
t
[mV]
VIN
VIN =
±250 mV = 500 mV diff
VIN or VINB double pad (pins 54, 55 or 56, 57)
VIN or VINB
50
reverse termination
500 mV
Full Scale
analog input
VINB = 0V
VINB
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