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參數(shù)資料
| 型號(hào)： | TS8388BVFSB/Q |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 37/47頁 |
| 文件大?。?/td> | 1230K |
| 代理商： | TS8388BVFSB/Q |
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42
TS8388BF
2144A–BDC–04/02
(JITTER) Aperture
Uncertainty
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the
slew rate of the signal at the sampling point.
(TS) Settling Time
Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step
function is applied to the differential analog input.
(ORT) Overvoltage
Recovery Time
Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input
is reduced to midscale.
(TOD) Digital Data
Output Delay
Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to
the next point of change in the differential output data (zero crossing) with specified load.
(TD1) Time Delay from
Data to Data Ready
Time delay from Data transition to Data ready.
(TD2) Time Delay from
Data Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock
period.
(TC) Encoding Clock
Period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
(TPD) Pipeline Delay
Number of clock cycles between the sampling edge of an input data and the associated output
data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4
clock periods.
(TRDR) Data Ready
Reset Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)
and the reset to digital zero transition of the Data Ready output signal (DR).
(TR) Rise Time
Time delay for the output DATA signals to rize from 20% to 80% of delta between low level
and high level.
(TF) Fall Time
Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and
high level.
(PSRR) Power Supply
Rejection Ratio
Ratio of input offset variation to a change in power supply voltage.
(NRZ) Non Return to
Zero
When the input signal is larger than the upper bound of the ADC input range, the output code
is identical to the maximum code and the Out of Range bit is set to logic one. When the input
signal is smaller than the lower bound of the ADC input range, the output code is identical to
the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input sig-
nal amplitude remains within the absolute maximum ratings).
(IMD) InterModulation
Distortion
The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the
worst third order intermodulation products. The input tones levels are at -7 dB Full Scale.
(NPR) Noise Power
Ratio
The NPR is measured to characterize the ADC performance in response to broad bandwidth
signals. When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the
average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output
sample test.
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| TS8388BCF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFB/T | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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| TS8388BMFS9NB3 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS8388BVGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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| TS83C196KB-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| TS83C196KD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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