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參數資料
| 型號： | TS8388BVFSB/Q |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 21/47頁 |
| 文件大小： | 1230K |
| 代理商： | TS8388BVFSB/Q |
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28
TS8388BF
2144A–BDC–04/02
Single-ended ECL
Clock Input
In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock
input pin CLKB (respectively CLK) connected to -1.3V through the 50
termination resistor.
The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode.
Figure 31. Single-ended Clocl Input (ECL):
VCLK Common Mode = -1.3V; VCLKB = -1.3V
Noise Immunity
Information
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible
to chip environment perturbations resulting from the circuit itself or induced by external cir-
cuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip)
decoupling capacitors).
Furthermore, the fully differential operation from analog input up to the digital outputs provides
enhanced noise immunity by common mode noise rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be can-
celed out by these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount
of coupled noise on the active inputs.
The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground
pins, which must be directly connected to the external ground plane.
Digital Outputs
The TS8388BF differential output buffers are internally 75
loaded. The 75 resistors are
The TS8388BF output buffers are designed for driving 75
(default) or 50 properly termi-
nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of
the 75
resistors when switching ensures a 0.825V voltage drop across the resistor (untermi-
nated outputs).
The V
PLUSD positive supply voltage allows the adjustment of the output common mode level
from -1.2V (V
PLUSD = 0V for ECL output compatibility) to +1.2V (VPLUSD = 2.4V for LVDS output
compatibility).
Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,
(outputs unterminated), around -1.2V common mode voltage.
-1.8V
-0.8V
t
[V]
VCLK
VCLKB = -1.3V
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