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參數(shù)資料
| 型號： | TS86101G2BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255 |
| 封裝： | HERMETIC SEALED, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 14/57頁 |
| 文件大小： | 1030K |
| 代理商： | TS86101G2BCGL |
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21
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Figure 5-1.
Device Pinout
5.2
Registering the Input Data
The 4 × 10-bit differential digital input data patterns (port A: [Ai_T, Ai_F], port B: [Bi_T, Bi_F], port C:
[Ci_T, Ci_F] and port D: [Di_T, Di_F]) are loaded in parallel into the first bank of master latches by the
rising edge (hold mode) of the differential Data Ready input (D_CK_T,D_CK_F).
Note:
The Data Ready duty cycle may vary in accordance with the setup and hold times. The digital data and
Data Ready input rates are equivalent to one fourth of the CW_IN master clock frequency. The Data Ready
rising edge must be (approximately) centered within the digital data input pulse – a minimum setup and
hold time between the data and Data Ready must be observed to ensure enough margin for the input data
time jitter and the different systematic skews amongst the data (trace lengths, package skew, etc.).
The registered input data is latched in the second bank of master/slave latches by the rising edge of the
CW_IN master clock divided by 4. For correct operation, a phase relation between Data Ready and the
CW_IN master clock input must be respected (see Figure 5-2).
Figure 5-2.
Data or Data Ready (D-CK) Timing
A0_T; A9_T
A0_F; A9_F
20
D_CK_T
D_CK_F
OUT_T
OUT_F
VEEA
TS86101G2B
DGND
DSP_CK_T
DSP_CK_F
VEED
B0_F; B9_F
B0_T; B9_T
C0_T; C9_T
C0_F; C9_F
D0_F; D9_F
D0_T; D9_T
AGND
VCCD
DIODE
CS_0 CS_3
CW_IN_T
CW_IN_F
20
2
4
Setup + hold time = 1.2 ns max
Hold time = 2.5 ns
Data
D_CK
AOUT
Data N
Data N+1
Data N
Data N+1
Setup time = -1.3 ns
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