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參數資料
型號: TS86101G2BCGL
廠商: E2V TECHNOLOGIES PLC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
封裝: HERMETIC SEALED, CERAMIC, BGA-255
文件頁數: 36/57頁
文件大小: 1030K
代理商: TS86101G2BCGL
41
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
12.3
CW_IN Master Clock Implementation
In order to allow for any ECL/PECL/LVDS differential input levels, the CW_IN master input clock must be
AC-coupled through 10 nF capacitors (for information only) as shown in Figure 12-8.
Figure 12-8. CW_IN Master Input Clock Implementation in AC-coupled Differential Mode
Figure 12-9. CW_IN Master Input Clock Implementation in AC-coupled Singled-ended Mode
12.4
DSP Output Clock Implementation
In order to make the DSP output clock compatible with standard differential levels such as LVDS and
PECL, the signals must be AC-coupled with 10 pF capacitors and used with pull-down resistors to
ensure appropriate biasing, as shown in the following three figures.
Three configurations are depicted:
The load has a high impedance input buffer
The load has a 100
Ω differential buffer
The DSP_CLK is sent to the load via a driver
CW_IN_T
CW_IN_F
VEEA
50
Ω
Driving
Source
10 nF
CW Input
Buffer
AGND
50
Ω
MUXDAC
50
Ω lines
500
Ω
450
Ω
-10 dBm (200 mVpp) to
+2 dBm (800 mVpp) max
-10 dBm (200 mVpp) to
+2 dBm (800 mVpp) max
CW_IN_T
CW_IN_F
VEEA
50
Ω
Driving
Source
10 nF
CW Input
Buffer
AGND
50
Ω
AGND
50
Ω
MUXDAC
50
Ω Lines
500
Ω
450
Ω
-4 dBm (400 mVpp) to
+8 dBm (1.6 Vpp) max
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