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參數資料
| 型號： | TS88915T |
| 英文描述： | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| 中文描述： | TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時鐘驅動器。 3國70和100兆赫的版本 |
| 文件頁數： | 10/19頁 |
| 文件大小： | 333K |
| 代理商： | TS88915T |
10
TS88915T
2122A–HIREL–06/02
5.
A 1 M
resistor tied to either Analog V
CC
or Analog GND as shown in Figure 5 is
required to ensure no jitter is present on the TS88915T outputs. This technique
causes a phase offset between the SYNC input and the output connected to the
FEEDBACK input, measured at the input pins. The T
PD
spec describes how this
offset varies with process, temperature and voltage. The specs are arrived at by
measuring the phase relationship for the 14 lots described in Note 1 while the
part was in phase-locked operation. The actual measurements are made with 10
MHz SYNC input (1.0 ns edge rate from 0.8V - 2.0V) with the Q/2 output feed
back. The phase measurements are made at 1.5V. The Q/2 output is terminated
at the FEEDBACK input with 100
to V
CC
and 100
to GND.
Figure 6.
Depiction of the Fixed SYNC to Feedback Offset (t
PD
) Which is Present When a 1 M
Resistor is Tied to V
CC
or GND
EXTERNAL LOOP
FILTER
6.
The t
SKEWr
specification guarantees that the rising edges of outputs Q/2, Q0, Q1,
Q2, Q3 and Q4 will always fall within a 500 ps window within one part. However,
if the relative position of each output within this window is not specified, the
500 ps window must be added to each side of the t
PD
specification limits to cal-
culate the total part-to-part skew. For this reason the absolute distribution of
these outputs is provided in Table 4. When taking the skew data, Q0 was used
as a reference, so all measurements are relative to this output. The information
in Table 4 is derived from measurements taken from the 14 process lots
described in Note 1, over the temperature and voltage range.
RC1
R2
330
C1
0.1
μ
F
ANALOG GND
1 M
REFERENCE
RESISTOR
1 M
REFERENCE
RESISTOR
RC1
330
0.1
μ
F
C1
SYNC INPUT
FEEDBACK OUTPUT
3.0V
5.0V
2.25 ns OFFSET
SYNC INPUT
FEEDBACK OUTPUT
-0.775 ns OFFSET
3.0V
5.0V
With the 1 M
resistor tied in this fashion, the tPD
specification measured at the input pins is:
tPD = 2.25 ns ± 1.0 ns
With the 1 M
resistor tied in this fashion, the tPD
specification measured at the input pins is:
tPD = -0.775 ns ± 0.275 ns
R2
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