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參數資料
| 型號： | TS88915T |
| 英文描述： | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| 中文描述： | TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時鐘驅動器。 3國70和100兆赫的版本 |
| 文件頁數： | 12/19頁 |
| 文件大小： | 333K |
| 代理商： | TS88915T |
12
TS88915T
2122A–HIREL–06/02
Figure 7.
9.
The Lock indicator pin (LOCK) will reliably indicate a phase-locked condition at
SYNC input frequencies down to 10 MHz. At frequencies below 10 MHz, the fre-
quency of correction pulses going into the phase detector from the SYNC and
FEEDBACK pins may not be sufficient to allow the lock indicator circuitry to
accurately predict a phase-locked condition. The TS88915T is guaranteed to
provide stable phase-locked operation down to the appropriate minimum input
frequency given in Table 3, even though the LOCK pin may be low at frequen-
cies below 10 MHz.
Timing Notes
1.
The TS88915T aligns rising edges of the FEEDBACK input and the SYNC input,
therefore the SYNC input does not require a 50% duty cycle.
All skew specs are measured between V
CC
/2 crossing point of the appropriate
output edges. All skews are specified as ‘windows’, not as a “deviation around a
center point”.
If a “Q” output is connected to the FEEDBACK input (this situation is not shown),
the “Q” output frequency would match the SYNC input frequency, the 2X_Q out-
2.
3.
tPD versus Frequency for Q/2 output feed back,
including process and voltage variation at 25°C
(with 1 M
resistor tied to analog VCC)
tPD versus Frequency for Q4 output feed back,
including process and voltage variation at 25°C
(with 1 M
resistor tied to analog VCC)
tPD versus Frequency for Q/2 output feed back,
including process and voltage variation at 25°C
(with 1 M
resistor tied to analog GND)
tPD versus Frequency for Q4 output feed back,
including process and voltage variation at 25°C
(with 1 M
resistor tied to analog GND)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
10
15
20
25
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
-0.50
-0.75
-1.00
-1.25
-1.50
-0.50
-1.00
-1.50
-2.00
2.5 5.0 7.5 10 12.5 15 17.5 20 22.5 25 27.5
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
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相關代理商/技術參數 |
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| TS88915TMR70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 29PGA RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMW70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 28LCCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMWB/T55 | 制造商:e2v technologies 功能描述: |
| TS88915TMWB/T70 | 制造商:e2v technologies 功能描述:PLL Clock Driver Single 35MHz to 70MHz 28-Pin LDCC |
| TS88915TVW100 | 功能描述:IC CLK DVR 8OUT PLL 28LCCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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