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參數資料
| 型號： | TS88915T |
| 英文描述： | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| 中文描述： | TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時鐘驅動器。 3國70和100兆赫的版本 |
| 文件頁數： | 11/19頁 |
| 文件大小： | 333K |
| 代理商： | TS88915T |
11
TS88915T
2122A–HIREL–06/02
7.
Calculation of Total Output-to-Output skew Between Multiple Parts (Part-to-Part
Skew)
By combining the t
PD
specification and the information in Note 5, the worst case
Output-to-Output skew between multiple TS88915’s connected in parallel can be
calculated. This calculation assumes that all parts have a common SYNC input
clock with equal delay that input signal to each part. This skew value is valid at
the TS88915 output pins only (equally loaded), it does not include PCB trace
delays due to varying loads.With a 1 M
resistor tied to analog VCC as shown in
Note 4, the t
PD
spec. limits between SYNC and the Q/2 output (connected to the
FEEDBACK pin) are -1.05 ns and -0.5 ns. To calculate the skew of any given
output between two or more parts, the absolute value of the distribution of that
output given in Table 4 must be subtracted and added to the lower and upper t
PD
spec limits respectively. For output Q2, [276-(-44)] = 320 ps is the absolute value
of the distribution. Therefore [-1.05 - 0.32] = -1.37 ns is the lower t
PD
limit, and [-
0.5 + 0.32] = -0.18 ns is the upper limit. Therefore the worst case skew of output
Q2 between any number of part is [(-1.37)-(-0.18)] = 1.19 ns. Q2 has the worst
case skew distribution of any output, so 1.2 ns is the absolute worst case Out-
put-to-Output skew between multiple parts.
Note 4 explains that the t
PD
specification was measured and is guaranteed for
the configuration of the Q/2 output connected to the FEEDBACK pin and the
SYNC input running at 10 MHz. The fixed offset (t
PD
) as described above has
some dependence on the input frequency and what frequency the VCO is run-
ning. The graphs of Figure 6 demonstrate this dependence. The data presented
in Figure 6 is from devices representing process extremes, and the measure-
ments were also taken at the voltage extremes (V
CC
= 5.25V and 4.75V).
Therefore the data in Figure 6 is a realistic representation of the variation of t
PD
.
8.
Table 4.
Relative Position of Outputs Q/2, Q0-Q4, 2X_Q,Within the 500 ps t
SKEWr
Spec
Window
Output
-
(ps)
+
(ps)
Q0
Q1
Q2
Q3
Q4
Q/2
2X_Q
0
-72
-44
-40
-274
-16
-633
0
40
275
255
-34
250
-35
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