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參數資料
| 型號： | TSB41AB3 |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 3個IEEE 1394a端口電纜收發器/仲裁器 |
| 文件頁數： | 17/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41AB3 |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions (Continued)
FIELD
SIZE
TYPE
DESCRIPTION
ISBR
1
Rd/Wr
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3
μ
s) arbitrated bus
reset at the next opportunity. This bit is reset to 0 by a bus reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs can not be capable of performing short bus resets.
Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus
reset being performed.
CTOI
1
Rd/Wr
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during tree-ID
start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing
a 1 to this register bit.
If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON
output to notify the LLC to service the interrupt.
NOTE: If the network is configured in a loop, only those nodes which are part of the loop generates a
configuration-timeout interrupt. Instead, all other nodes time out waiting for the tree-ID and/or self-ID process
to complete and then generate a state time-out interrupt and bus-reset.
CPSI
1
Rd/Wr
Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating
that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared
by writing a 1 to this register bit.
If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON
output to notify the LLC to service the interrupt.
STOI
1
Rd/Wr
State-timeout interrupt. This bit indicates that a state time-out has occurred (which also causes a bus-reset to
occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit.
If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON
output to notify the LLC to service the interrupt.
PEI
1
Rd/Wr
Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port
for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE) bit is
set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset,
or by writing a 1 to this register bit.
EAA
1
Rd/Wr
Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration
enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation,
and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset.
NOTE: The EAA bit is set only if the attached LLC is 1394a-2000 compliant. If the LLC is not 1394a-2000
compliant, use of the arbitration acceleration enhancements can interfere with isochronous traffic by
excessively delaying the transmission of cycle-start packets.
EMC
1
Rd/Wr
Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of
differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware
reset and is unaffected by bus reset.
NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE
Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be
1394a-2000 compliant.
Page_Select
3
Rd/Wr
Page_Select. This field selects the register page to use when accessing register addresses 8 through 15.
This field is reset to 0 by a hardware reset and is unaffected by bus-reset.
Port_Select
4
Rd/Wr
Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the port
status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by
hardware-reset and is unaffected by bus-reset.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41AB3-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41AB3IPFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3IPFP | 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP |
| TSB41AB3IPFPEP | 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
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