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參數資料
| 型號： | TSB41AB3 |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 3個IEEE 1394a端口電纜收發器/仲裁器 |
| 文件頁數： | 21/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41AB3 |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal register configuration (continued)
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
NPA
1
Rd/Wr
Null-packet actions flag. This bit instructs the PHY to not clear fair and priority requests when a null packet is
received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when a
packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and
malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0, then fair and priority
requests are cleared when any nonACK packet is received, including null-packets or malformed packets of
less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus-reset.
Link_Speed
2
Rd/Wr
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY
and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer
PHYs during self-ID; the TSB41AB3 PHY identifies itself as S400 capable to its peers regardless of the value
in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
SWR
1
Rd/Wr
Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (just as momentarily asserting the
RESET pin low). This bit is always read as a 0.
power-class programming
The PC0
–
PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field
(bits 21
–
23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 9
The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently
loaded into the Pwr_Class field in register 4.
Table 9. Power Class Descriptions
PC0
–
PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self-powered and provides a minimum of 15 W to the bus.
010
Node is self-powered and provides a minimum of 30 W to the bus.
011
Node is self-powered and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W and may also provide power to the bus. The amount of bus power that
it provides can be found in the configuration ROM.
101
Reserved
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB41BA3-EP | IC APEX 20KE FPGA 400K 672-FBGA |
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB41AB3-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A-2000 THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41AB3IPFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3IPFP | 制造商:Texas Instruments 功能描述:IC TRX/ARBITER 1394A 3 PORT 80HTQFP |
| TSB41AB3IPFPEP | 功能描述:1394 接口集成電路 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
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