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參數(shù)資料
| 型號： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 45/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41BA3-EP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation
(ISO terminal is low) is as follows:
1
a.
Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
b.
LPS deasserted. The LLC deasserts the LPS signal and, within 1
μ
s, terminates any request or interface
bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC terminates
any output signal activity such that signals end in a logic 0 state).
c.
Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface
is now in the reset state.
d.
Interface disabled. If the LPS signal remain inactive for T
LPS_DISABLE
time, the PHY terminates
SYSCLK activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface
is now in the disabled state.
SYSCLK
ISO
(High)
(a)
(c)
(b)
CTL0, CTL1
D0
–
D7
LREQ
LPS
TLPS_RESET
(d)
TLPS_DISABLE
Figure 25. Interface Disable, ISO High
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