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參數資料
| 型號： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強塑料的IEEE 1394b三端口電纜收發器/仲裁器 |
| 文件頁數： | 46/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41BA3-EP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
46
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of operation
(ISO terminal is high) is as follows:
1
a.
Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
LPS deasserted. The LLC deasserts the LPS signal and, within 1
μ
s, terminates any request or interface
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset
state.
Interface disabled. If the LPS signal remain inactive for T
LPS_DISABLE
time, the PHY terminates
SYSCLK activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.
After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal
operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 26 and
Figure 27.
b.
c.
d.
SYSCLK
ISO
(Low)
(a)
(c)
(b)
CTL0
D0
–
D7
LREQ
LPS
(d)
TCLK_ACTIVATE
CTL1
7 Cycles
5 ns. min
10 ns. max
Figure 26. Interface Initialization, ISO Low
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