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參數資料
| 型號： | U6268B-FP |
| 英文描述： | Low power JFET dual operational amplifiers |
| 文件頁數： | 5/13頁 |
| 文件大小： | 109K |
| 代理商： | U6268B-FP |
U6268B
Rev. A3, 11-Apr-01
5 (13)
ENABLE1, ENABLE2
ENABLEx is a microcontroller-compatible input which
switches the related output on or off.
Low or open circuit applied to ENABLEx switches off
the related OUTx and RETURNx (high impedance).
A sink current at Pin OUTx discharges the capacitive
load.
High applied to ENABLEx switches on the related
OUTx and RETURNx to supply the external unit.
OCM1, OCM2
The output current of OUTx is monitored with a transmis-
sion factor of 0.1 to the OCMx. With a resistor from OCM
to GND, the current is converted to a voltage. The electri-
cal characteristics are specified by R
OCM
= 750 . The
CLL-current threshold, the OUT-current limitation and
the OUT-current detection can be changed by varying
R
OCM
in a range from 500 to 1 k .
The current monitoring enables to detect overcurrent
conditions at OUTx (short circuit to GND or RETURNx)
and to detect low current conditions at OUTx (short cir-
cuit to V
Batt
or open load).
The internal pull-down current at the OUTx creates no
OCMx-current. During enable, the minimum voltage at
OCMx is the saturation voltage of an internal NPN-tran-
sistor with typically 0.1 V. The maximum voltage at
OCM is limited by an internal clamping diode to 5.3 V.
CLL1, CLL2
The
current at Pin OUTx is evaluated logically and ready
to use for a microcontroller input. With this stage, the
logic data transmission from the external unit to the inter-
face is completed.
CLLx is the output stage of a comparator with an internal
threshold and with the OCMx input. A OCMx-voltage
higher than 2.4 V creates a logic low at CLLx, and a
OCMx-voltage lower than 1.43 V creates a logic high at
CLLx. The comparator has an internal hysteresis with
typically 0.4 V.
With the pull-down resistor R
OCMx
= 750 at OCMx, the
correct OUTx-current threshold related to the logical out-
put CLLx is ensured. The CLLx is ’low’ if the
OUTx-current is higher than 27.3 mA, and the CLLx is
’high’, if the OUTx-current is lower than 19.1 mA. The
comparator has an internal hysteresis of typically 5 mA.
The tolerance of the R
OCM
resistor is assumed to be 0%.
The CLL-pin is an open-collector output and needs a
pull-up resistor of typically 2 k to the 5-V supply. For
ESD protection, a 7-V Zener diode is implemented.
RETURN 1, RETURN 2
The RETURNx pin provides a low-ohmic connection to
GND via a switched open-collector NPN-transistor. If
ENABLEx is high, RETURNx is switched on with a satu-
ration voltage less than 0.5 V at I
RETURNx
ENABLEx is low or open, RETURNx is a current sink
with
2 mA. RETURNx is current-limited at typically
150 mA.
SC
50 mA. If
The smooth capacitor is designed to realize the long-time
constant for the slow voltage change at OUTx for both in-
terface channels. The capacity is typ. 22 nF. At the rising
edge of V
Batt
, the maximum slew rate is V
OUTx
= 5 V/ms,
and at the falling edge of V
Batt
, the maximum slew rate
is V
OUTx
= 10 V/ms.
GND-Pins
By means of a GND bond from the chip to Pin 1 and Pin 8,
high ground breakage security is achieved and lowest
voltage drop and ground shift between IC- and circuit
ground is provided. The four GND pins and the die pad
are directly connected to the copper leadframe, resulting
in a very low thermal resistance, R
thJC
. In order to achieve
a good thermal resistance, R
thJA,
a good copper connec-
tion from the four GND pins to the metal parts of the
modul housing is also recommended.
Power Dissipation
Worst case calculation of the supply current I
S
:
I
S
= 1,278
( I
OUT1
+ I
OUT2
) + 18 mA
Worst case calculation of the IC’s power dissipation P
V
:
P
V
= (V
S
I
S
) – [(V
S
– V
diff
– V
ret-sat
)
+R
OCM
((I
OUT12
+ I
OUT22
) / 81)]
(I
OUT1
+ I
OUT2
)
V
S
V
diff
= 5.7 to 25 V supply voltage
= V
S
to V
OUTx
voltage difference
V
diff
= 3.6 V at 12 V
V
diff
= 0.8 V at 5.7 V
V
ret-sat
= 0.5 V saturation voltage return
I
OUTx
= output current at Pin OUTx = 0 to 60 mA
R
OCM
= resistor at Pin OCMx
An overtemperature protection is integrated which gene-
rates a switch-off signal at a chip temperature of typically
T
j
= 160
°
C and a switch-on signal at typically T
j
= 150
°
C.
V
S
V
S
25 V
8.5 V
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