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參數資料
| 型號： | UDA1352HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 48 kHz IEC 60958 audio DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數： | 26/64頁 |
| 文件大小： | 262K |
| 代理商： | UDA1352HL |
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2003 Mar 25
26
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
11 SPDIF SIGNAL FORMAT
11.1
SPDIF channel encoding
The digital signal is coded using Bi-phase Mark Code
(BMC) which is a type of phase-modulation. In this
scheme, a logic 1 in the data corresponds to two
zero-crossings in the coded signal, and a logic 0
corresponds to one zero-crossing. An example of the
encoding is given in Fig.11.
From an abstract point of view, an SPDIF signal can be
represented as shown in Fig.12. Audio or digital data is
transmitted in sequential blocks. Each block comprises
192 frames. Each frame contains two sub-frames.
Each sub-frame is preceded by a preamble word, of which
there are three types: B, M and W. Preamble B signifies
the start of channel 1 at the start of a data block,
M signifies the start of channel 1 that is not at the start of a
data block, and W signifies the start of channel 2. Each of
these preamble words can have one of two values
depending on the value of the parity bit in the previous
frame.
Preambles are easily identifiable because these
sequences can never occur in the channel parts of a valid
SPDIF stream, see Table 14.
The SPDIF signal format used for audio data (PCM mode)
and digital data (non-PCM mode) are different. However,
both formats have a validity bit that indicates whether the
sample is valid, a user data bit, a channel status bit, and a
parity bit in each sub-frame.
11.2
SPDIF hierarchical layers for audio data
A two-channel PCM signal uses one sub-frame per
channel.
Each sub-frame contains a single 20-bit audio sample
which can extend to 24 bits (see Fig.13).
Data bits 4 to 31 in each sub-frame are modulated using a
BMC scheme. Sync preamble bits 0 to 3 contain a
violation of the BMC scheme to allow them to be easily
identified.
Table 14
Preamble values
11.3
SPDIF hierarchical layers for digital data
For transmitting non-PCM data, the IEC 60958 protocol
allocates the time slot bits shown in Table 15 to each
sub-frame.
Table 15
Bit allocation of digital data
As shown in Table 15 and Fig.14, the non-PCM encoded
data occurs within the 16-bit data stream area of the
IEC 60958 sub-frame in time-slots 12 (LSB) to 27 (MSB).
handbook, halfpage
clock
data
BMC
MGU606
Fig.11 Bi-phase mark encoding.
PRECEDING
PARITY BIT
VALUE
PREAMBLE WORD
B
M
W
0
1
1110 1000
0001 0111
1110 0010
0001 1101
1110 0100
0001 1011
FIELD
IEC 60958TIME
SLOT BITS
DESCRIPTION
0 to 3
4 to 7
8 to 11
12 to 27
preamble
auxiliary bits
unused data bits
part of 16-bit
data
validity bit
user data bit
channel status
bit
parity bit
IEC 60958 preamble
not used; all logic 0
not used; all logic 0
part of the digital
bitstream
according to IEC 60958
according to IEC 60958
according to IEC 60958
28
29
30
31
according to IEC 60958
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1352TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:48 kHz IEC 60958 audio DAC |
| UDA1352TS/N3 | 制造商:NXP Semiconductors 功能描述:IC DAC AUDIO 48KHZ 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, DAC, AUDIO, 48KHZ, 28-SSOP, Resolution (Bits):20bit, Input Channel Type:Seri |
| UDA1352TS/N3,112 | 功能描述:音頻數/模轉換器 IC DAC 2CH Interpolatio Filter 28-Pin RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| UDA1352TS/N3,118 | 功能描述:數模轉換器- DAC DAC 2CH Interpolatio Filter 28-Pin RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| UDA1352TS/N3112 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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