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參數資料
| 型號： | UDA1380 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | 立體聲音頻編碼器，可用于MD，CD和MP3解碼器 |
| 文件頁數： | 42/68頁 |
| 文件大小： | 278K |
| 代理商： | UDA1380 |
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2002 Sep 16
42
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.10 Mixer, silence detector and oversampling settings
Table 46
Register address 14H
Table 47
Description of register bits
BIT
15
14
13
12
11
0
10
0
9
0
8
0
Symbol
Default
DA_POL_INV
0
SEL_NS
0
MIX_POS
0
MIX
0
BIT
7
6
5
4
3
0
2
0
1
0
Symbol
Default
SILENCE
0
SDET_ON
0
SD_VALUE1
0
SD_VALUE0
0
OS1
0
OS0
0
BIT
SYMBOL
DESCRIPTION
15
DA_POL_INV
DAC polarity control.
A 1-bit value to control the signal polarity of the
DAC output signal. When this bit is logic 0: DAC output not inverted.
When this bit is logic 1: DAC output inverted. Default value 0.
Noise shaper order select.
A 1-bit value to select between the
3rd-order and the 5th-order noise shaper. When this bit is logic 0: select
3rd-order noise shaper. When this bit is logic 1: select 5th-order noise
shaper. Default value 0.
Mixer signal control.
A 2-bit value to select the digital mixer settings
inside the interpolation filter. Default value 0. Default the mixer is off,
see Table 48.
default value 0000
Silence detector.
A 1-bit value to force the DAC output to silence.
When this bit is logic 0: no overruling. The setting of the FSDAC silence
switch depends on the status of the digital silence detector circuit and
the master_mute status. When this bit is logic 1: overruling. The FSDAC
silence switch is activated, independent of the status of the digital
silence detector circuit or the master_mute status. Default value 0.
Silence detector enable.
A 1-bit value to enable the digital silence
detector. When this bit is logic 0: silence detection circuit disabled.
When this bit is logic 1: silence detection circuit enabled. Default
value 0.
Silence detector settings.
A 2-bit value to program the silence
detector, the number of ‘ZERO’ samples counted before the silence
detector signals whether there has been digital silence. Default
value 00, see Table 49.
default value 00
Oversampling input settings.
A 2-bit value to select the oversampling
input mode. Default value 00, see Table 50.
14
SEL_NS
13
12
MIX_POS
MIX
11 to 8
7
SILENCE
6
SDET_ON
5 and 4
SD_VALUE[1:0]
3 and 2
1 and 0
OS[1:0]
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1380HN | 制造商:ICS 制造商全稱:ICS 功能描述:Stereo audio coder-decoder for MD, CD and MP3 |
| UDA1380HN/N2 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO MINIDISC 32HVQFN 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, MINIDISC, 32HVQFN |
| UDA1380HN/N2,118 | 功能描述:接口—CODEC STEREO AUDIO RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380HN-T | 功能描述:接口—CODEC STEREO AUDIO CODER-DECODER RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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