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參數資料
| 型號： | UDA1380TT |
| 元件分類： | 通用總線功能 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | 立體聲音頻編碼器，可用于MD，CD和MP3解碼器 |
| 文件頁數： | 14/68頁 |
| 文件大小： | 278K |
| 代理商： | UDA1380TT |
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2002 Sep 16
14
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
In applications in which a 2 V (RMS) input signal is used,
a12 k
resistormustbeusedinserieswiththeinputofthe
ADC (see Fig.7). This forms a voltage divider together with
the internal ADC resistor and ensures that the voltage,
applied to the input of the IC, never exceeds 1 V (RMS).
Using this application for a 2 V (RMS) input signal, the
switch must be set to 0 dB. When a 1 V (RMS) input signal
is applied to the ADC in the same application, the gain
switch must be set to 6 dB.
An overview of the maximum input voltages allowed
againstthepresenceof anexternal resistorand thesetting
of the gain switch is given in Table 2; the power supply
voltage is assumed to be 3 V.
Table 2
Application modes using input gain stage
8.3
Decimation filter (ADC)
The decimation from 128f
s
is performed in two stages. The
first stage realizes a
characteristic with a decimation
factor of 16. The second stage consists of 3 half-band
filters, each decimating by a factor 2. The filter
characteristics are shown in Table 3.
Table 3
Decimation filter characteristics
8.3.1
O
VERLOAD DETECTION
TheUDA1380isequippedwithanoverloaddetectorwhich
can be read out from the L3-bus or I
2
C-bus interface.
In practice the output is used to indicate whenever the
output data, in either the output of the left or right channel,
exceeds
1 dB (the actual figure is
1.16 dB) of the
maximum possible digital swing. When this condition is
detected the output bit OVERFLOW in the L3-bus register
is forced to logic 1 for at least 512f
s
cycles (11.6 ms at
f
s
= 44.1 kHz). This time-out is reset for each infringement.
8.3.2
V
OLUME CONTROL
The decimator is equipped with a digital volume control.
This volume control is separate for left and right and can
be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via
the L3-bus or I
2
C-bus interface. The range is from +24 dB
to
63.5 dB and mutes in steps of 0.5 dB.
8.3.3
M
UTE
The decimator is equipped with a dB-linear mute which
mutes the signal in 256 steps of 0.5 dB.
8.3.4
AGC
FUNCTION
The decimation filter is equipped with an AGC block. This
function is intended, when enabled, to keep the output
signal at a constant level. The AGC can be used for
microphone applications in which the distance to the
microphone is not always the same.
The AGC can be enabled via an L3-bus or I
2
C-bus bit by
setting the bit to logic 1. In that case it bypasses the digital
volume control.
Via the L3-bus or I
2
C-bus interface also some other
settings of the AGC, like the attack and decay settings and
the target level settings, can be made.
Remark
: The DC filter before the decimation filter must be
enabled by setting the L3-bus or I
2
C-bus bit SKIP_DCFIL
to logic 0 when AGC is in operation; otherwise the output
will be disturbed by the DC offset added in the ADC.
RESISTOR
(12 k
)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present
0 dB
6 dB
0 dB
6 dB
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
Absent
handbook, halfpage
MGU529
VREF
VDDA = 3 V
VINL,
VINR
31,
1
(27,
29)
PGA
12 k
external
resistor
12 k
input signal
2 V (RMS)
Fig.7 ADC front-end with PGA (line input).
Pin numbers for UDA1380HN in parentheses.
x
sin
---x
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
Stop band
Dynamic range
Digital output
level
0 to 0.45f
s
>0.55f
s
0 to 0.45f
s
at 0 dB input
analog
0.01
70
>135
1.5
相關PDF資料 |
PDF描述 |
|---|---|
| UDA1384 | Multichannel audio coder-decoder |
| UDA1384H | Multichannel audio coder-decoder |
| UDN2878W-2 | 10A SCRS |
| UDZ2.4B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| UDZ10B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
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