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參數資料
型號: UDA1380TT
元件分類: 通用總線功能
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數: 3/68頁
文件大小: 278K
代理商: UDA1380TT
2002 Sep 16
3
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
1
FEATURES
1.1
General
2.4 to 3.6 V power supply
5 V tolerant digital inputs (at 2.4 to 3.6 V power supply)
24-bit data path for Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
Selectable control via L3-bus microcontroller interface
or I
2
C-bus interface; choice of 2 device addresses in
L3-bus and I
2
C-bus mode
Remark
: This device does not have a static mode
Supports sample frequencies from 8 to 55 kHz for the
ADC part, and 8 to 100 kHz for the DAC part. The ADC
cannot support DVD audio (96 kHz audio), only
Mini-Disc (MD), Compact-Disc (CD) and Moving Picture
Experts Group Layer-3 Audio (MP3). For playback
8 to 100 kHz is specified. DVD playback is supported
Power management unit:
– Separate power control for ADC, Automatic Volume
Control (AVC), DAC, Phase Locked Loop (PLL) and
headphone driver
– Analog blocks like ADC and Programmable Gain
Amplifier (PGA) have a block to power-down the bias
circuits
– When ADC and/or DAC are powered-down, also the
clocks to these blocks are stopped to save power
Remark:
By default, when the IC is powered-up, the
complete chip will be in the Power-down mode.
ADC part and DAC part can run at different frequencies,
either system clock or Word Select PLL (WSPLL)
ADC and PGA plus integrated high-pass filter to cancel
DC offset
The decimation filter is equipped with a digital Automatic
Gain Control (AGC)
Mono microphone input with Low Noise Amplifier (LNA)
of 29 dB fixed gain and Variable Gain Control (VGA)
from 0 to 30 dB in steps of 2 dB
Integrated digital filter plus DAC
Separate single-ended line output and one stereo
headphone output, capable of driving a 16
load. The
headphone driver has a built-in short-circuit protection
with status bits which can be read out from the
L3-bus or I
2
C-bus interface
Digital silence detection in the interpolator (playback)
with read-out status via L3-bus or I
2
C-bus interface
Easy application.
1.2
Multiple format data input interface
Slave BCK and WS signals
I
2
S-bus format
MSB-justified format compatible
LSB-justified format compatible.
1.3
Multiple format data output interface
Select option for digital output interface: either the
decimatoroutput(ADC signal)ortheoutputsignalofthe
digital mixer which is in the interpolator DSP
Selectable master or slave BCK and WS signals for
digital ADC output
Remark
:SYSCLKmustbeappliedinWSPLLmodeand
master mode
I
2
S-bus format
MSB-justified format compatible
LSB-justified format compatible.
1.4
ADC front-end features
ADC plus decimator can run at either WSPLL,
regenerating the clock from WSI signal, or on SYSCLK
Stereo line input with PGA: gain range from 0 to 24 dB
in steps of 3 dB
LNA with 29 dB fixed gain for mono microphone input,
including VGA with gain from 0 to 30 dB in steps of 2 dB
Digital left and right independent volume control and
mute from +24 to
63.5 dB in steps of 0.5 dB.
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相關代理商/技術參數
參數描述
UDA1380TT/N2 制造商:PHILIP 功能描述:
UDA1380TT/N2,512 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1380TT/N2,518 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1380TT-T 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1384 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multichannel audio coder-decoder
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