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參數資料
| 型號： | UDA1384 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Multichannel audio coder-decoder |
| 中文描述： | 多聲道音頻編碼解碼器 |
| 文件頁數： | 21/55頁 |
| 文件大小： | 276K |
| 代理商： | UDA1384 |
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9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
21 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
A slave receiver which is addressed, must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse, so the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse. Set-up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
10.8 Device address
Before any data is transmitted on the I
2
C-bus, the device which should respond is
addressed first. The addressing is always done with byte 1 transmitted after the start
procedure. The UDA1384 acts as a slave receiver or a slave transmitter.
Therefore, the clock signal SCL is only an input signal. The data signal SDA is a
bidirectional line. The UDA1384 device address is shown in
Table 17
.
10.9 Register address
The register addresses in the I
2
C-bus mode are the same as in the L3-bus mode. The
register addresses are defined in
Section 11
.
10.10 Write and read data
The I
2
C-bus configurations for a write and read cycle are shown in
Table 18
and
Table 19
,
respectively.
Fig 15. Acknowledge on the I
2
C-bus
mbc602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
Table 17:
Device address
A6
0
I
2
C-bus device address of UDA1384
R/W
A5
0
A4
1
A3
1
A2
0
A1
0
A0
0
0/1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1384H | 功能描述:編碼器、解碼器、復用器和解復用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H/N1,518 | 功能描述:編碼器、解碼器、復用器和解復用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H/N1,557 | 功能描述:編碼器、解碼器、復用器和解復用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H-T | 功能描述:編碼器、解碼器、復用器和解復用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1431T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit, 48 kHz, low-cost stereo current DAC |
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