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參數資料
| 型號： | W25P010A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 32K×32 Burst Pipeline High-Speed CMOS Static RAM(32K×32位同步脈沖式管高速CMOS靜態RAM) |
| 中文描述： | 32K的管道爆裂× 32高速CMOS靜態RAM（32K的× 32位同步脈沖式管高速的CMOS靜態RAM）的 |
| 文件頁數： | 4/17頁 |
| 文件大?。?/td> | 314K |
| 代理商： | W25P010A |
W25P010A
- 4 -
FUNCTIONAL DESCRIPTION
The W25P010A is a synchronous-burst pipelined, SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel
systems and linear mode, which can
be controlled by the
LBO
pin. The burst cycles are initiated by ADSP or ADSC and the burst
counter is incremented whenever ADV is sampled low. The device can also be switched to non-
pipelined mode if necessary.
BURST ADDRESS SEQUENCE
INTEL SYSTEM (LBO = V
DDQ
)
A[1:0]
A[1:0]
00
01
01
00
10
11
11
10
LINEAR MODE (LBO= V
SSQ
)
A[1:0]
A[1:0]
00
01
01
10
10
11
11
00
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
External Start Address
Second Address
Third Address
Fourth Address
The device supports several types of write mode operations. BWE and BW [4:1] support individual
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW [4:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-Out
Read
相關PDF資料 |
PDF描述 |
|---|---|
| W25P012A | 32K×32 Burst Pipeline High-Speed CMOS Static RAM(32K×32位同步脈沖管線高速CMOS靜態RAM) |
| W25P022A | 64K×32 Burst Pipeline High-Speed CMOS Static RAM(64K×32位同步脈沖管線高速CMOS靜態RAM) |
| W25P022A-6 | 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P022A-7 | 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P022AF-6 | 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W25P010AD-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AD-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AD-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AF-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
| W25P010AF-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Fast Synchronous SRAM |
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