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參數(shù)資料
型號: W25P010A
廠商: WINBOND ELECTRONICS CORP
英文描述: 32K×32 Burst Pipeline High-Speed CMOS Static RAM(32K×32位同步脈沖式管高速CMOS靜態(tài)RAM)
中文描述: 32K的管道爆裂× 32高速CMOS靜態(tài)RAM(32K的× 32位同步脈沖式管高速的CMOS靜態(tài)RAM)的
文件頁數(shù): 5/17頁
文件大小: 314K
代理商: W25P010A
W25P010A
Publication Release Date: September 1996
- 5 -
Revision A7
Truth Table, continued
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-Out
Read
Begin Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
X
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled
to the bus clock except for the OE pin.
synchronous
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup
SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold timings are
met.
he
WRITE TABLE
READ/WRITE FUNCTION
Read
Read
Write byte 1 I/O1
I/O8
Write byte 2 I/O9
I/O16
Write byte 2, byte 1
Write byte 3 I/O17
I/O24
Write byte 3, byte 1
Write byte 3, byte 2
Write byte 3, byte 2, byte 1
Write byte 4 I/O25
I/O32
Write byte 4, byte 1
GW
1
1
1
1
1
1
1
1
1
1
1
BWE
1
0
0
0
0
0
0
0
0
0
0
BW4
X
1
1
1
1
1
1
1
1
0
0
BW3
X
1
1
1
1
0
0
0
0
1
1
BW2
X
1
1
0
0
1
1
0
0
1
1
BW1
X
1
0
1
0
1
0
1
0
1
0
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