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參數資料
| 型號： | 70V659S10DR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 DUAL-PORT SRAM, 10 ns, PQFP208 |
| 封裝： | 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208 |
| 文件頁數： | 7/24頁 |
| 文件大小： | 316K |
| 代理商： | 70V659S10DR |
15
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol
Parameter
70V659/58/57S10
Com'l Only
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY
TIMING (M/S=VIH)
tBAA
BUSY
Access Time from Address Match
____
10
____
12
____
15
ns
tBDA
BUSY
Disable Time from Address Not Matched
____
10
____
12
____
15
ns
tBAC
BUSY
Access Time from Chip Enable Low
____
10
____
12
____
15
ns
tBDC
BUSY
Disable Time from Chip Enable High
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
5
____
ns
tBDD
BUSY
Disable to Valid Data(3)
____
10
____
12
____
15
ns
tWH
Write Hold After BUSY(5)
8
____
10
____
12
____
ns
BUSY
TIMING (M/S=VIL)
tWB
BUSY
Input to Write(4)
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
8
____
10
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
22
____
25
____
30
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
20
____
22
____
25
ns
4869 tbl 14
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 70V659S10DRG | 功能描述:IC SRAM 4MBIT 208QFP 制造商:idt, integrated device technology inc 系列:* 零件狀態:在售 標準包裝:6 |
| 70V659S12BC | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 4.5M-Bit 128K x 36 12ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 4.5MBIT 128KX36 12NS 256BGA - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:128Kx36 STD-PWR 3.3V DUAL-PORT RAM |
| 70V659S12BC8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 4.5M-Bit 128K x 36 12ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 4.5MBIT 128KX36 12NS 256BGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:128Kx36 STD-PWR 3.3V DUAL-PORT RAM |
| 70V659S12BCGI | 功能描述:靜態隨機存取存儲器 128Kx36 STD-PWR 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V659S12BCI | 功能描述:靜態隨機存取存儲器 128Kx36 STD-PWR 3.3V DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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