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參數資料
型號: 70V659S10DR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 DUAL-PORT SRAM, 10 ns, PQFP208
封裝: 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
文件頁數: 8/24頁
文件大小: 316K
代理商: 70V659S10DR
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
16
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4869 drw 12
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
tBAA
.
4869 drw 13
R/
W"A"
BUSY"B"
tWB
(3)
R/
W"B"
tWH
(1)
(2)
tWP
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