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參數資料
| 型號： | 71M6543H-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數： | 17/157頁 |
| 文件大小： | 2178K |
| 代理商： | 71M6543H-IGTR/F |
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71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
113
Name
Location Rst Wk Dir
Description
PLL_OK
SFR F9[4]
0
R
Indicates that the clock generation PLL is settled.
PLL_FAST
2200[4]
0
R/W
Controls the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0]
210A[7:0] FF FF R/W
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if
PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is
(2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in units of CK_FIR
clock cycles. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse
width checking is performed and the output pulses have 50% duty cycle. See 2.3.6.2
VPULSE and WPULSE.
PLS_INTERVAL[7:0]
210B[7:0]
0
R/W
PLS_INTERVAL[7:0] determines the interval time between pulses. The time between
output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If
PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE
issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0] = Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux
frame / 4 )
For example, since the 71M6543 CE code is written to generate 6 pulses in one integration
interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0]
≠ 0) and that the frame
duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with
Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the
integration interval and the last pulse is issued just prior to the end of the interval. See
2.3.6.2 VPULSE and WPULSE.
PLS_INV
210C[0]
0
R/W
Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low.
When inverted, they become active high. PLS_INV has no effect on XPULSE or
YPULSE.
PORT_E
270C[5]
0
R/W
Enables outputs from the SEGDIO0-SEGDIO15 pins. PORT_E = 0 blocks the momentary
output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up.
PRE_E
2704[5]
0
R/W
Enables the 8x pre-amplifier.
PREBOOT
SFRB2[7]
–
R
Indicates that pre-boot sequence is active.
RCMD[4:0]
SFR FC[4:0] 0
0
R/W
When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to
the appropriate remote sensor. When the command is complete, the 71M6543 clears
RCMD.
RESET
2200[3]
0
W
When set, writes a one to WF_RSTBIT and then causes a reset.
RFLY_DIS
210C[3]
0
R/W
Controls how the 71M6543 drives the power pulse for the 71M6xxx. When set, the
power pulse is driven high and low. When cleared, it is driven high followed by an open
circuit fly-back interval.
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| 71M6545HT-IGT/F | 制造商:Maxim Integrated Products 功能描述:METROLOGY PROCESSORS - Rail/Tube |
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