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參數資料
| 型號： | 73S1209F-68IMR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數： | 121/123頁 |
| 文件大小： | 1385K |
| 代理商： | 73S1209F-68IMR/F |
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DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
97
CRC MS Value Registers (CRCMsB): 0xFE14
0xFF, (CRCLsB): 0xFE15
0xFF
Table 94: The CRCMsB Register
MSB
LSB
CRC.15
CRC.14
CRC.13
CRC.12
CRC.11
CRC.10
CRC.9
CRC.8
Table 95: The CRCLsB Register
MSB
LSB
CRC.7
CRC.6
CRC.5
CRC.4
CRC.3
CRC.2
CRC.1
CRC.0
The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode
(read value). The initial value of CRC to be used when generating a CRC to be transmitted at the end of
a message (after the last TX byte is sent) when enabled in T=1 mode. Should be reloaded at the
beginning of every message to be transmitted. When using CRC, the both CRC registers should be
initialized to FF. When using LRC the CRCLsB Value register should be loaded to 00. When receiving a
message, the firmware should load this with the initial value and then read this register to get the final
value at the end of the message. These registers need to be reloaded for each new message to be
received. When in LRC mode, bits (7:0) are used and bits (15:8) are undefined. During LRC/CRC
checking and generation, this register is updated with the current value and can be read to aid in
debugging. This information will be transmitted to the smart card using the timing specified by the Guard
Time register. When checking CRC/LRC on an incoming message (CRC/LRC is checked against the
data and CRC/LRC), the firmware reads the final value after the message has been received and
determines if an error occurred (= 0x1D0F (CRC_ no error, else error; = 0 (LRC) no error, else error).
When a message is received, the CRC/LRC is stored in the FIFO. The polynomial used to generate and
check CRC is x
16 + x12+ x5 +1. When in indirect convention, the CRC is generated prior to the conversion
into indirect convention. When in indirect convention, the CRC is checked after the conversion out of
indirect convention. For a given message, the CRC generated (and readable from this register) will be
the same whether indirect or direct convention is used to transmit the data to the smart card. The
CRCLsB / CRCMsB registers will be updated with CRC/LRC whenever bits are being received or
transmitted from/to the smart card (even if CRCEN is not set and in mode T1). They are available to the
firmware to use if desired.
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相關代理商/技術參數 |
參數描述 |
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| 73S1209F-68M/F/P1 | 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| 73S1209F-EB | 功能描述:開發板和工具包 - 8051 73S1209F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
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