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參數(shù)資料
| 型號： | 73S1209F-68IMR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 封裝： | LEAD FREE, QFN-68 |
| 文件頁數(shù)： | 83/123頁 |
| 文件大小： | 1385K |
| 代理商： | 73S1209F-68IMR/F |
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73S1209F Data Sheet
DS_1209F_004
12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the MCLKCtl register (see the Oscillator
and Clock Generation section) to carry out scanning and debouncing. The keypad size can be adjusted
within the KSIZE register.
Normal scanning is performed by hardware when the SCNEN bit is set to 1 in the KSTAT register. Figure
12 shows the flowchart of how the hardware scanning operates. In order to minimize power, scanning
does not occur until a key-press is detected. Once hardware key scanning is enabled, the hardware
drives all column outputs low and waits for a low to be detected on one of the inputs. When a low is
detected on any row, and before key scanning starts, the hardware checks that the low level is still
detected after a debounce time. The debounce time is defined by firmware in the KSCAN register (bits
7:0, DBTIME). Debounce times from 4ms to 256ms in 4ms increments are supported. If a key is not
pressed after the debounce time, the hardware will go back to looking for any input to be low. If a key is
confirmed to be pressed, key scanning begins.
Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating
that a key is pressed at the intersection of the drive/sense line in the keypad. After all sense lines have
been checked without a key-press being detected, the next column line is asserted. The time between
checking each sense line is the scan time and is defined by firmware in the KSCAN register (bits 0:1 –
SCTIME). Scan times from 1ms to 4ms are supported. Scanning order does not affect the scan time.
This scanning continues until the entire keypad is scanned. If only one key is pressed, a valid key is
detected. Simultaneous key presses are not considered as valid (If two keys are pressed, no key is
reported to firmware).
registers that define the order of column scanning. Values in these registers must be updated every time
a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines.
The column and row intersection for the detected valid key are stored in the KCOL and KROW registers.
When a valid key is detected, an interrupt is generated. Firmware can then read those registers to
after a valid key has been identified. The hardware does not wait for the firmware to service the interrupt
in order to proceed with the key scanning process. Once the valid key (or invalid key – e.g. two keys
pressed) is detected, the hardware waits for the key to be released. Once the key is released, the
debounce timer is started. If the key is not still released after the debounce time, the debounce counter
starts again. After a key release, all columns will be driven low as before and the process will repeat
waiting for any key to be pressed.
When the SCNEN bit is disabled, all drive outputs are set to the value in the KCOL register. If firmware
clears the SCNEN bit in the middle of a key scan, the KCOL register contains the last value stored in
there which will then be reflected on the output pins.
A bypass mode is provided so that the firmware can do the key scanning manually (SCNEN bit must be
cleared). In bypass mode, the firmware writes/reads the Column and Row registers to perform the key
scanning.
62
Rev. 1.2
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PDF描述 |
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| 73S1209F-68IM/F | POWER SUPPLY MANAGEMENT CKT, QCC68 |
| 73S1209F-44IMR/F | POWER SUPPLY MANAGEMENT CKT, QCC44 |
| 73S1209F-44IM/F | POWER SUPPLY MANAGEMENT CKT, QCC44 |
| 73S1210F-44IMR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC44 |
| 73S1210F-68IM/F/P | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73S1209F-68M/F/P1 | 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| 73S1209F-EB | 功能描述:開發(fā)板和工具包 - 8051 73S1209F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
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