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參數資料
型號: A3PE1500-PQG208
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數: 106/152頁
文件大小: 4932K
代理商: A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
v1.2
2 - 45
SSTL3 Class II
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class II. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-71 Minimum and Maximum DC Input and Output Levels
SSTL3 Class II
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min., V Max., V
Min., V
Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
21 mA
–0.3
VREF – 0.2 VREF + 0.2
3.6
0.5
VCCI – 0.9 21 21
109
103
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-20 AC Loading
Table 2-72 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.5
1.485
30
* Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
30 pF
25
SSTL3
Class II
VTT
Table 2-73 SSTL3 Class II
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI =3.0 V, VREF = 1.5 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
–F
0.79
2.48
0.05
1.50
0.51
2.53
2.01
5.21
4.69
ns
Std.
0.66
2.07
0.04
1.25
0.43
2.10
1.67
4.34
3.91
ns
–1
0.56
1.76
0.04
1.06
0.36
1.79
1.42
3.69
3.32
ns
–2
0.49
1.54
0.03
0.93
0.32
1.57
1.25
3.24
2.92
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
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相關代理商/技術參數
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