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參數資料
型號: A3PE1500-PQG208
元件分類: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數: 97/152頁
文件大小: 4932K
代理商: A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
v1.2
2 - 37
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
2.5 V.
Timing Characteristics
Table 2-47 Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
IIH
Drive
Strength Min., V
Max., V
Min., V
Max., V Max., V Min., V mA mA Max., mA1 Max., mA1
μA2 μA2
25 mA3
–0.3
VREF – 0.05 VREF + 0.05
3.6
0.4
25 25
124
169
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Figure 2-12 AC Loading
Table 2-48 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.05
VREF + 0.05
0.8
1.2
10
* Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
10 pF
25
GTL
VTT
Table 2-49 2.5 V GTL
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI =3.0 V VREF = 0.8 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
–F
0.72
2.56
0.05
2.95
0.51
2.60
2.56
5.28
5.24
ns
Std.
0.60
2.13
0.04
2.46
0.43
2.16
2.13
4.40
4.36
ns
–1
0.51
1.81
0.04
2.09
0.36
1.84
1.81
3.74
3.71
ns
–2
0.45
1.59
0.03
1.83
0.32
1.61
1.59
3.28
3.26
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
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相關代理商/技術參數
參數描述
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