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參數資料
| 型號： | A3PE1500-PQG208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 38400 CLBS, 1500000 GATES, PQFP208 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 |
| 文件頁數： | 149/152頁 |
| 文件大小： | 4932K |
| 代理商： | A3PE1500-PQG208 |
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ProASIC3E DC and Switching Characteristics
2- 84
v1.2
Advance v0.6
(continued)
Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
The "VPUMP Programming Supply Voltage" section was updated.
2-50
The "GL Globals" section was updated to include information about direct
input into quadrant clocks.
2-51
VJTAG was deleted from the "TCK Test Clock" section.
2-51
In Table 2-22 Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
2-51
Ambient was deleted from Table 3-2 Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
Note 3 is new in Table 3-4 Overshoot and Undershoot Limits (as measured
on quiet I/Os).
3-2
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
3-5
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-5
Table 3-5 Package Thermal Resistivities was updated.
3-5
Table 3-10 Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
3-8
tWRO and tCCKH were added to Table 3-94 RAM4K9 and Table
3-95 RAM512X18.
3-74 to
3-74
The note in Table 3-24 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure
3-43 Write
Access
After
Write
onto
Same
Address,
Figure
3-44 Read Access After Write onto Same Address, and Figure 3-45 Write
Access After Read onto Same Address are new.
3-71 to
3-73
Figure 3-53 Timing Diagram was updated.
3-80
Advance v0.4
(October 2005)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-8 Very-Long-Line Resources was updated.
2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated.
2-28
The Delay Increments in the Programmable Delay Blocks specification in
Figure 2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Introduction" section was updated.
2-28
Previous Version
Changes in Current Version (v1.2)
Page
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A3PE1500-PQG208I | 功能描述:IC FPGA 1KB FLASH 1.5M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:ProASIC3E 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數:9360 邏輯元件/單元數:149760 RAM 位總計:6635520 輸入/輸出數:270 門數:- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23） |
| A3PE1500-PQG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE1500-PQG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
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