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參數資料
| 型號： | AD7679CB1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| 中文描述： | 18位，2.5 LSB INL和570 kSPS的SAR型ADC |
| 文件頁數： | 19/28頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD7679CB1 |
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AD7679
Power Supply
The AD7679 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines the
output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 25. The AD7679 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range (see Figure 30).
Rev. 0 | Page 19 of 28
SAMPLING RATE (SPS)
1000000
P
μ
W
1M
100000
10000
1000
100
10
1
0.1
100k
10k
1k
100
1
10
PDBUFHIGH
03085-0-033
FREQUECY (kHz)
65
P
40
100
1000
10000
1
10
60
55
50
45
03085-0-032
Figure 31. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 32 shows the detailed timing diagrams of the conversion
process. The AD7679 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by PD, until the conversion is complete. The
CNVST signal operates independently of CS and RD.
CNVST
t
1
t
2
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
t
7
t
8
BUSY
t
4
t
3
t
5
t
6
03085-0-034
Figure 30. PSRR vs. Frequency
POWER DISSIPATION VERSUS THROUGHPUT
The AD7679 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows for a
significant power savings when the conversion rate is reduced,
as shown in Figure 31. This feature makes the AD7679 ideal for
very low power battery applications.
Figure 32. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be
driven close to the power rails (DVDD and DGND), and
OVDD should not exceed DVDD by more than 0.3 V.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock it with a high
frequency low jitter clock, as shown in Figure 25.
For other applications, conversions can be automatically
initiated. If CNVST is held low when BUSY is low, the AD7679
controls the acquisition phase and automatically initiates a new
conversion. By keeping CNVST low, the AD7679 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7679 could sometimes
run slightly faster than the guaranteed limits of 570 kSPS.
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